公开(公告)号：US06523093B1

公开(公告)日：2003-02-18

申请号：US09675893

申请日：2000-09-29

申请人： Zohar Bogin ,  Steven Clohset

发明人： Zohar Bogin ,  Steven Clohset

IPC分类号： G06F1200

CPC分类号： G06F12/0862 ,  G06F2212/6022

摘要： A system is described for prefetching data from a main memory before the data is requested by a processor. The system includes a prefetch buffer having a number of entries to store prefetch reads. Each entry in the prefetch buffer includes a storage area designated for data and address. The system also includes a number of state machines, each state machine to track data phase for each entry in the prefetch buffer. A read request controller is coupled to the prefetch buffer and is configured to receive a read request from the processor or I/O devices and controls dispatching of prefetch requests to a main memory.

摘要翻译： 描述了在处理器请求数据之前从主存储器预取数据的系统。 该系统包括具有多个条目以存储预取读取的预取缓冲器。 预取缓冲器中的每个条目包括指定用于数据和地址的存储区域。 该系统还包括多个状态机，每个状态机为了预取缓冲器中的每个条目跟踪数据阶段。 读取请求控制器耦合到预取缓冲器，并且被配置为从处理器或I / O设备接收读取请求并且控制将预取请求分派到主存储器。

公开(公告)号：US06314472B1

公开(公告)日：2001-11-06

申请号：US09203127

申请日：1998-12-01

申请人： Tuong P. Trieu ,  David D. Lent ,  Ashish S. Gadagkar ,  Vincent E. VonBokern ,  Zohar Bogin

发明人： Tuong P. Trieu ,  David D. Lent ,  Ashish S. Gadagkar ,  Vincent E. VonBokern ,  Zohar Bogin

IPC分类号： G06F300

CPC分类号： G06F13/161

摘要： A computer system is provided. The computer system includes a host processor (HP), a system memory (SM), and an input/output (I/O) master device to perform a read of a continuous stream of data to the SM. The computer system also includes a bridge coupled to the HP, SM, and I/O master device. The bridge reads ahead to the SM when the I/O master device reads a continuous stream of data from the SM. The bridge aborts read ahead accesses to the SM, prior to an access commit point to the SM, responsive to disengagement of the I/O master device.

摘要翻译： 提供计算机系统。 计算机系统包括主机处理器（HP），系统存储器（SM）以及输入/输出（I / O）主设备，以执行对SM的连续数据流的读取。 计算机系统还包括耦合到HP，SM和I / O主设备的桥。 当I / O主设备从SM读取连续的数据流时，桥接器向前读取SM。 响应于I / O主设备的脱离接口，桥接器在对SM进行访问提交之前中止对SM的预读访问。

公开(公告)号：US06141283A

公开(公告)日：2000-10-31

申请号：US285998

申请日：1999-04-01

申请人： Zohar Bogin ,  David E. Freker

发明人： Zohar Bogin ,  David E. Freker

IPC分类号： G06F1/32 ,  G11C7/10 ,  G11C8/00 ,  G11C7/00

CPC分类号： G06F1/3225 ,  G06F1/3275 ,  G11C7/1045 ,  G11C7/1072 ,  G11C8/00 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/32

摘要： An apparatus and method for dynamically placing portions of a memory in a reduced power consumption state. Requests to access a memory that includes a plurality of rows of memory components are received. One or more of the plurality of rows of memory components are placed in a reduced power consumption state based on the requests while one or more other rows of the plurality of rows are accessed.

摘要翻译： 一种用于在降低的功耗状态下动态地放置存储器的部分的装置和方法。 接收到访问包括多行存储器组件的存储器的请求。 所述多行存储器组件中的一个或多个在所述多个行中的一个或多个其他行被访问的同时，基于所述请求被置于降低的功耗状态。

公开(公告)号：US5655127A

公开(公告)日：1997-08-05

申请号：US612673

申请日：1996-03-08

申请人： Jeffrey L. Rabe ,  Zohar Bogin ,  Ajay V. Bhatt ,  James P. Kardach ,  Nilesh V. Shah

发明人： Jeffrey L. Rabe ,  Zohar Bogin ,  Ajay V. Bhatt ,  James P. Kardach ,  Nilesh V. Shah

IPC分类号： G06F1/32 ,  G06F1/26

CPC分类号： G06F1/3209 ,  G06F1/3203 ,  G06F1/3287 ,  Y02B60/1282 ,  Y02B60/32

摘要： A computer system having a responsive low-power mode and a full-power mode of operation. The computer system includes a power consumption controller, a processor and a communication device. The power consumption controller generates an interrupt signal in response to a low power event or a fully operational event. The power consumption controller also generates a clock control signal. The clock control signal is deasserted during the full-power mode of operation and alternatively asserted for a first duration and deasserted for a second duration during the low-power mode of operation. In response to an asserted clock control signal, the processor suppresses the internal clock signal to at least one functional block within the processor and in response to a deasserted clock control signal, the processor transmits the internal clock signal to at least one functional block within the processor. By transmitting the internal clock signal to at least one functional block within the processor during the low-power mode of operation, the processor may respond to communication signals from a communication device during the low-power mode of operation.

摘要翻译： 一种具有响应低功率模式和全功率工作模式的计算机系统。 计算机系统包括功率消耗控制器，处理器和通信设备。 功率消耗控制器响应于低功率事件或完全运行的事件而产生中断信号。 功耗控制器还产生时钟控制信号。 时钟控制信号在全功率工作模式期间被断言，并且在低功率操作模式期间另行断言第一持续时间并且断言第二持续时间。 响应于断言的时钟控制信号，处理器将内部时钟信号抑制到处理器内的至少一个功能块，并且响应于无效时钟控制信号，处理器将内部时钟信号发送到内部时钟信号中的至少一个功能块 处理器。 通过在低功率操作模式期间将内部时钟信号发送到处理器内的至少一个功能块，处理器可以在低功率操作模式期间响应来自通信设备的通信信号。

公开(公告)号：US07797492B2

公开(公告)日：2010-09-14

申请号：US10783621

申请日：2004-02-20

申请人： Anoop Mukker ,  Zohar Bogin ,  Tuong Trieu ,  Aditya Navale

发明人： Anoop Mukker ,  Zohar Bogin ,  Tuong Trieu ,  Aditya Navale

IPC分类号： G06F13/16

CPC分类号： G06F12/121 ,  G06F12/0862 ,  G06F12/128

摘要： A method and apparatus for dedicating cache entries to certain streams for performance optimization are disclosed. The method according to the present techniques comprises partitioning a cache array into one or more special-purpose entries and one or more general-purpose entries, wherein special-purpose entries are only allocated for one or more streams having a particular stream ID.

摘要翻译： 公开了用于将高速缓存条目专用于某些流以用于性能优化的方法和装置。 根据本技术的方法包括将高速缓存阵列划分成一个或多个特殊用途条目和一个或多个通用条目，其中仅为具有特定流ID的一个或多个流分配专用条目。

公开(公告)号：US07672178B2

公开(公告)日：2010-03-02

申请号：US11648855

申请日：2006-12-29

申请人： Suryaprasad Kareenahalli ,  Zohar Bogin

发明人： Suryaprasad Kareenahalli ,  Zohar Bogin

IPC分类号： G11C7/00

CPC分类号： G06F13/4054

摘要： An integrated circuit communicates with memory devices. Data from the memory devices arrives at the integrated circuit with varying propagation delays. The integrated circuit detects the arrival of data from the memory devices, and stores the data in FIFOs. A FIFO drain signal is generated responsive to the detection of the data arrival.

摘要翻译： 集成电路与存储器件通信。 来自存储器件的数据到达具有变化的传播延迟的集成电路。 集成电路检测来自存储器件的数据的到达，并将数据存储在FIFO中。 响应于数据到达的检测而产生FIFO漏极信号。

公开(公告)号：US07620833B2

公开(公告)日：2009-11-17

申请号：US11633183

申请日：2006-12-04

申请人： Chai Huat Gan ,  Darren Abramson ,  Zohar Bogin

发明人： Chai Huat Gan ,  Darren Abramson ,  Zohar Bogin

IPC分类号： G06F1/32

CPC分类号： G06F1/3225

摘要： For isochronous data steams processed by a computer system, for example high definition audio streams, embodiments keep track of the free space available in the input and output buffers for the data streams. The available free space in the buffers determines whether various low power entry and exit thresholds are met or not. If all low power entry thresholds are met, then various circuits such as clocks, phase locked loops, and direct media interface links, may be put into a low power state, and the data stream controller enters an idle window so that memory requests are not serviced. During this time, system DRAM may begin refresh. Once the low power state has been entered into, if any exit threshold is met, then the low power state is ended. Other embodiments are described and claimed.

摘要翻译： 对于由计算机系统处理的等时数据流，例如高清晰度音频流，实施例跟踪用于数据流的输入和输出缓冲器中的可用空间。 缓冲器中的可用空间确定是否满足各种低功率进入和退出阈值。 如果满足所有低功率入口阈值，则诸如时钟，锁相环和直接介质接口链路的各种电路可能被置于低功率状态，并且数据流控制器进入空闲窗口，使得存储器请求不是 服务。 在此期间，系统DRAM可能会开始刷新。 一旦输入低功率状态，如果满足任何退出阈值，则低功率状态结束。 描述和要求保护其他实施例。

公开(公告)号：US07587547B2

公开(公告)日：2009-09-08

申请号：US11394461

申请日：2006-03-30

申请人： Chee Hak Teh ,  Suryaprasad Kareenahalli ,  Zohar Bogin

发明人： Chee Hak Teh ,  Suryaprasad Kareenahalli ,  Zohar Bogin

IPC分类号： G06F12/00

CPC分类号： G06F13/161 ,  G06F12/0215

摘要： The invention describes a technology for closing DRAM pages, wherein the invention allows for dynamically changing code streams by tracking the previous decisions made on page closes and adjusts dynamically during DRAM operation to compensate for bad page close decisions made.

摘要翻译： 本发明描述了一种用于关闭DRAM页面的技术，其中本发明允许通过跟踪在页面关闭时做出的先前决定来动态地改变代码流，并且在DRAM操作期间动态调整以补偿所做出的错误页面关闭决定。

公开(公告)号：US07409516B2

公开(公告)日：2008-08-05

申请号：US11394462

申请日：2006-03-30

申请人： Chee Hak Teh ,  Suryaprasad Kareenahalli ,  Zohar Bogin

发明人： Chee Hak Teh ,  Suryaprasad Kareenahalli ,  Zohar Bogin

IPC分类号： G06F12/00

CPC分类号： G06F13/1668 ,  G06F12/0215

摘要： Embodiments of a memory scoreboard are presented herein. The memory scoreboard tracks memory requests for each rank and bank of memory being addressed. When there are no pending requests, the scoreboard provides an indication to an idle timer that begins a count down to close a current page of the memory. The idle timer can be configured dynamically to close memory pages and to address dynamically-changing code streams by tracking previous decisions made on page closes.

摘要翻译： 记忆记分板的实施例在本文中给出。 记忆记分板跟踪正在寻址的每个等级和存储体的存储器请求。 当没有未决请求时，记分板向空闲计时器提供指示，该空闲计时器开始向下计数以关闭存储器的当前页面。 可以动态配置空闲计时器以关闭内存页面，并通过跟踪页面关闭时做出的以前决定来解决动态变化的代码流。

公开(公告)号：US20080162852A1

公开(公告)日：2008-07-03

申请号：US11647985

申请日：2006-12-28

申请人： Surya Kareenahalli ,  Zohar Bogin

发明人： Surya Kareenahalli ,  Zohar Bogin

IPC分类号： G06F13/00

CPC分类号： G06F12/0215

摘要： A method, apparatus, and system are described. In one embodiment, the method comprises a chipset receiving a plurality of memory requests, wherein each memory request comprises one or more micro-commands that each require one or more memory clock cycles to execute, and scheduling the execution of each of the micro-commands from more than one of the plurality of memory requests in an order to reduce the number of total memory clock cycles required to complete execution of the more than one memory requests.

摘要翻译： 描述了一种方法，装置和系统。 在一个实施例中，该方法包括接收多个存储器请求的芯片组，其中每个存储器请求包括一个或多个微命令，每个微命令需要一个或多个存储器时钟周期来执行，并且调度每个微命令的执行 从多个存储器请求中的多于一个的顺序，以减少完成执行多于一个存储器请求所需的总存储器时钟周期的数量。