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    Microelectromechanical device with integrated package
    61.
    发明授权
    Microelectromechanical device with integrated package 有权
    具有集成封装的微机电装置

    公开(公告)号：US08791557B2

    公开(公告)日：2014-07-29

    申请号：US13652999

    申请日：2012-10-16

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Allen Timothy Chang ,  Yi-Shao Liu ,  Ching-Ray Chen ,  Chun-Ren Cheng

    IPC: H01L23/02

    CPC classification number: G01N21/648 ,  G01N21/6454 ,  H01L23/02 ,  H01L24/80 ,  H01L2924/12042 ,  H01L2924/12043 ,  Y10T156/10 ,  H01L2924/00

    Abstract: A BioMEMS microelectromechanical apparatus and for fabricating the same is disclosed. A substrate is provided with at least one signal conduit formed on the substrate. A sacrificial layer of sacrificial material may be deposited on the signal conduit and optionally patterned to remove sacrificial material from outside the packaging covered area. A bonding layer may be deposited on at least a portion of the signal conduit and on the sacrificial layer when included. The bonding layer may be planarized and patterned to form one or more cap bonding pads and define a packaging covered area. A cap may be bonded on the cap bonding pad to define a capped area and so that the signal conduit extends from outside the capped area to inside the capped area. Additionally, a test material such as a fluid may be provided within the capped area.

    Abstract translation: 公开了一种BioMEMS微机电装置及其制造方法。 衬底上设置有形成在衬底上的至少一个信号导管。 牺牲材料的牺牲层可以沉积在信号导管上，并且可选地被图案化以从包装覆盖区域的外部去除牺牲材料。 当包括的时候，粘结层可沉积在信号导管的至少一部分上和牺牲层上。 结合层可以被平坦化和图案化以形成一个或多个帽接合焊盘并限定包装覆盖区域。 帽可以结合在盖接合垫上以限定封盖区域，并且使得信号导管从封盖区域的外部延伸到封盖区域的内部。 此外，可以在封盖区域内设置诸如流体的测试材料。

    PIEZOELECTRIC ANTI-STICTION STRUCTURE FOR MICROELECTROMECHANICAL SYSTEMS
    63.
    发明申请
    PIEZOELECTRIC ANTI-STICTION STRUCTURE FOR MICROELECTROMECHANICAL SYSTEMS 有权

    公开(公告)号：US20250122071A1

    公开(公告)日：2025-04-17

    申请号：US19002880

    申请日：2024-12-27

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Fan Hu ,  Chun-Ren Cheng ,  Hsiang-Fu Chen ,  Wen-Chuan Tai

    IPC: B81B3/00 ,  B81C1/00

    Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a first dielectric structure disposed over a first semiconductor substrate, where the first dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the first dielectric structure and includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. A first piezoelectric anti-stiction structure is disposed between the movable mass and the first dielectric structure, wherein the first piezoelectric anti-stiction structure includes a first piezoelectric structure and a first electrode disposed between the first piezoelectric structure and the first dielectric structure

    HYBRID ULTRASONIC TRANSDUCER SYSTEM
    65.
    发明公开
    HYBRID ULTRASONIC TRANSDUCER SYSTEM 审中-公开

    公开(公告)号：US20230302494A1

    公开(公告)日：2023-09-28

    申请号：US17832937

    申请日：2022-06-06

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Ching-Hui Lin ,  Yi-Hsien Chang ,  Chun-Ren Cheng ,  Fu-Chun Huang ,  Yi Heng Tsai ,  Shih-Fen Huang ,  Chao-Hung Chu ,  Po-Chen Yeh

    IPC: B06B1/02 ,  B06B1/06

    CPC classification number: B06B1/0292 ,  B06B1/0622

    Abstract: The present disclosure relates to an integrated chip structure. The integrated chip structure includes a dielectric stack disposed on a substrate. The integrated chip structure further includes one or more piezoelectric ultrasonic transducers (PMUTs) and one or more capacitive ultrasonic transducers (CMUTs). The one or more PMUTs include a piezoelectric stack disposed within the dielectric stack over one or more PMUT cavities. The one or more CMUTs include electrodes disposed within the dielectric stack and separated by one or more CMUT cavities. An isolation chamber is arranged within the dielectric stack laterally between the one or more PMUTs and the one or more CMUTs. The isolation chamber vertically extends past at least a part of both the one or more PMUTs and the one or more CMUTs.

    Hybrid ultrasonic transducer and method of forming the same
    66.
    发明授权
    Hybrid ultrasonic transducer and method of forming the same 有权

    公开(公告)号：US11508902B2

    公开(公告)日：2022-11-22

    申请号：US17194107

    申请日：2021-03-05

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    Inventor： Yi Heng Tsai ,  Fu-Chun Huang ,  Ching-Hui Lin ,  Chun-Ren Cheng

    IPC: H01L41/27 ,  B81B7/02 ,  B06B1/02 ,  B06B1/06 ,  B81C3/00 ,  H01L41/113 ,  H01L41/29

    Abstract: A method of manufacturing a semiconductor device includes: forming a first substrate includes a membrane stack over a first dielectric layer, the membrane stack having a first electrode, a second electrode over the first electrode and a piezoelectric layer between the first electrode and the second electrode, a third electrode over the first dielectric layer, and a second dielectric layer over the membrane stack and the third electrode; forming a second substrate, including: a redistribution layer (RDL) over a third substrate, the RDL having a fourth electrode; and a first cavity on a surface of the RDL adjacent to the fourth electrode; forming a second cavity in one of the first substrate and the second substrate; and bonding the first substrate to the second substrate.

    Hybrid ultrasonic transducer and method of forming the same
    68.
    发明授权
    Hybrid ultrasonic transducer and method of forming the same 有权

    公开(公告)号：US10944041B1

    公开(公告)日：2021-03-09

    申请号：US16573833

    申请日：2019-09-17

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    Inventor： Yi Heng Tsai ,  Fu-Chun Huang ,  Ching-Hui Lin ,  Chun-Ren Cheng

    IPC: H01L41/27 ,  H01L41/113 ,  B81B7/02 ,  B06B1/02 ,  B06B1/06 ,  B81C3/00 ,  H01L41/29

    Abstract: A hybrid ultrasonic transducer and a method of manufacturing the same are provided. A method of manufacturing a semiconductor device includes the forming of a first substrate and a second substrate. The forming of the first substrate includes: depositing a membrane stack over a first dielectric layer; forming a third electrode over the first dielectric layer; and depositing a second dielectric layer over the membrane stack and the third electrode. The forming of the second substrate includes: forming a redistribution layer (RDL) having a fourth electrode; and etching a first cavity on a surface of the RDL adjacent to the fourth electrode. The method further includes: forming a second cavity in one of the first substrate and the second substrate; and bonding the first substrate to the second substrate.

    Semiconductor structure and manufacturing method thereof
    69.
    发明授权
    Semiconductor structure and manufacturing method thereof 有权

    公开(公告)号：US10737931B2

    公开(公告)日：2020-08-11

    申请号：US14815220

    申请日：2015-07-31

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    Inventor： Yi-Hsien Chang ,  Chun-Ren Cheng ,  Wei-Cheng Shen ,  Wen-Chien Chen

    IPC: B81B3/00

    Abstract: A semiconductor structure includes a first device and a second device. The first device includes a plate including a plurality of apertures; a membrane disposed opposite to the plate and including a plurality of corrugations, and a conductive plug extending through the plate and the membrane. The second device includes a substrate and a bond pad disposed over the substrate, wherein the conductive plug is bonded with the bond pad to integrate the first device with the second device, and the plate includes a semiconductive member and a tensile member, and the semiconductive member is disposed within the tensile member.

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