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公开(公告)号：US20250056874A1
公开(公告)日：2025-02-13
申请号：US18512452
申请日：2023-11-17
Inventor： Hung-Li Chiang , Ching-Hui Lin , Chun-Ren Cheng , Iuliana Radu
IPC: H01L27/092 , B82Y15/00 , H01L29/08 , H01L29/66
Abstract: One aspect of the present disclosure pertains to a device. The device includes a substrate, a logic circuit disposed on the substrate, and a nanoelectromechanical systems (NEMS) device electrically connected to the logic circuit and formed on the substrate. The NEMS device includes a first electrode electrically connected to the logic circuit, a second electrode electrically connected to a first power supply, a movable feature electrically connected to the second electrode, and a control electrode operable to move the movable feature relative to the first electrode.
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2.发明公开公开(公告)号：US20240290541A1
公开(公告)日：2024-08-29
申请号：US18659337
申请日：2024-05-09
Inventor： Anderson Lin , Chun-Ren Cheng , Chi-Yuan Shih , Shih-Fen Huang , Yi-Chuan Teng , Yi Heng Tsai , You-Ru Lin , Yen-Wen Chen , Fu-Chun Huang , Fan Hu , Ching-Hui Lin , Yan-Jie Liao
IPC: H01G4/012 , H01G4/12 , H01G4/228 , H01L21/311 , H01L21/3213 , H10N30/30 , H10N30/50 , H10N30/87
CPC classification number: H01G4/012 , H01G4/12 , H01G4/228 , H01L21/31111 , H01L21/32139 , H01L28/60 , H10N30/302 , H10N30/501 , H10N30/508 , H10N30/872
Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first conductive structure and a second conductive structure. A dielectric structure is arranged between the first conductive structure and the second conductive structure. The dielectric structure comprises an upper region over a lower region. The lower region comprises a first lateral surface and a second lateral surface on opposing sides of the upper region. A passivation layer overlies the second conductive structure and the dielectric structure. The passivation layer comprises a lateral segment contacting the first lateral surface. A height of the lateral segment is greater than a height of the upper region. A top surface of the lateral segment is below a top surface of the passivation layer.
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公开(公告)号：US11581308B2
公开(公告)日：2023-02-14
申请号：US16923925
申请日：2020-07-08
Inventor： Fu-Chun Huang , Ching-Hui Lin , Chun-Ren Cheng , Shih-Fen Huang , Alexander Kalnitsky
IPC: H01L27/07 , H01L29/06 , H01L49/02 , H01L21/8234 , H01L21/762
Abstract: A method for manufacturing a semiconductor structure is provided, wherein the method includes the following operations. A substrate having a transistor is received, wherein the transistor includes a channel region and a gate on a first side of the channel region. A second side of the channel region of the transistor is exposed, wherein the second side is opposite to the first side. A metal oxide is formed on the second side of the channel region of the transistor, wherein the metal oxide contacts the channel region and is exposed to the environment. A semiconductor structure and an operation of a semiconductor structure thereof are also provided.
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4.发明申请公开(公告)号：US20240397828A1
公开(公告)日：2024-11-28
申请号：US18321268
申请日：2023-05-22
Inventor： Ching-Hui Lin , Yi-Hsien Chang , Chun-Ren Cheng , Shih-Fen Huang , Fu-Chun Huang , Chao-Hung Chu , Po-Chen Yeh
IPC: H10N30/87 , H10N30/057 , H10N30/063 , H10N30/072 , H10N30/50
Abstract: Various embodiments of the present disclosure are directed towards a piezoelectric device including a piezoelectric structure over a substrate. A first conductive structure is disposed on a lower surface of the piezoelectric structure. The first conductive structure includes one or more first movable elements directly contacting the piezoelectric structure. A second conductive structure is disposed on an upper surface of the piezoelectric structure. The second conductive structure includes one or more second movable elements directly contacting the piezoelectric structure. The one or more second movable elements directly overlie the one or more first movable elements.
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公开(公告)号：US20220376164A1
公开(公告)日：2022-11-24
申请号：US17880773
申请日：2022-08-04
Inventor： Ching-Hui Lin , Chun-Ren Cheng , Shih-Fen Huang , Fu-Chun Huang
IPC: H01L41/113 , G01N27/414 , H01L41/33 , H01L41/053 , H01L41/27 , H01L41/047
Abstract: In some embodiments, a piezoelectric biosensor is provided. The piezoelectric biosensor includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A sensing reservoir is disposed over the piezoelectric structure and exposed to an ambient environment, where the sensing reservoir is configured to collect a fluid comprising a number of bio-entities.
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Patent Agency Ranking
公开(公告)号：US10756086B1
公开(公告)日：2020-08-25
申请号：US16281950
申请日：2019-02-21
Inventor： Fu-Chun Huang , Ching-Hui Lin , Chun-Ren Cheng , Shih-Fen Huang , Alexander Kalnitsky
IPC: H01L27/07 , H01L29/06 , H01L49/02 , H01L21/8234 , H01L21/762
Abstract: A method of manufacturing a semiconductor structure is provided, wherein the method includes the following operations. A substrate having a transistor is received, wherein the transistor includes a channel region and a gate on a first side of the channel region. The second side of the channel region of the transistor is exposed, wherein the second side is opposite to the first side. A metal oxide is formed on the second side of the channel region of the transistor, wherein the metal oxide contacts the channel region and is exposed to the environment. A semiconductor structure and an operation of a semiconductor structure thereof are also provided.
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公开(公告)号：US12029130B2
公开(公告)日：2024-07-02
申请号：US17880773
申请日：2022-08-04
Inventor： Ching-Hui Lin , Chun-Ren Cheng , Shih-Fen Huang , Fu-Chun Huang
IPC: H01L41/113 , G01N27/414 , H10N30/05 , H10N30/08 , H10N30/30 , H10N30/87 , H10N30/88
CPC classification number: H10N30/302 , G01N27/4141 , H10N30/05 , H10N30/08 , H10N30/878 , H10N30/88
Abstract: In some embodiments, a piezoelectric biosensor is provided. The piezoelectric biosensor includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A sensing reservoir is disposed over the piezoelectric structure and exposed to an ambient environment, where the sensing reservoir is configured to collect a fluid comprising a number of bio-entities.
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公开(公告)号：US11897759B2
公开(公告)日：2024-02-13
申请号：US17838023
申请日：2022-06-10
Inventor： Po Chen Yeh , Yi-Hsien Chang , Fu-Chun Huang , Ching-Hui Lin , Chiahung Liu , Shih-Fen Huang , Chun-Ren Cheng
CPC classification number: B81B7/007 , B81C1/00301 , B81B2201/0271 , B81B2203/0127 , B81B2207/012 , B81B2207/07 , B81B2207/097 , B81C2203/0792
Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first device and a second device disposed adjacent to the first device; a conductive pillar disposed adjacent to the first device or the second device; a molding surrounding the first device, the second device and the conductive pillar; and a redistribution layer (RDL) over the first device, the second device, the molding and the conductive pillar, wherein the RDL electrically connects the first device to the second device and includes an opening penetrating the RDL and exposing a sensing area over the first device.
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公开(公告)号：US20230387164A1
公开(公告)日：2023-11-30
申请号：US17824183
申请日：2022-05-25
Inventor： Yi-Hsien Chang , Shih-Fen Huang , Chun-Ren Cheng , Fu-Chun Huang , Ching-Hui Lin
IPC: H01L27/146
CPC classification number: H01L27/14627 , H01L27/14621 , H01L27/14678 , H01L27/14685 , H01L27/14629 , A61B5/68
Abstract: The present disclosure relates to an integrated chip including a semiconductor layer and a photodetector disposed along the semiconductor layer. A color filter is over the photodetector. A micro-lens is over the color filter. A dielectric structure comprising one or more dielectric layers is over the micro-lens. A receptor layer is over the dielectric structure. An optical signal enhancement structure is disposed along the dielectric structure and between the receptor layer and the micro-lens.
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公开(公告)号：US09958443B2
公开(公告)日：2018-05-01
申请号：US15581673
申请日：2017-04-28
Inventor： Ching-Hui Lin , Chun-Ren Cheng , Shih-Fen Huang , Yi-Hsien Chang
IPC: H01L51/05 , G01N27/414 , G01N33/543 , H01L29/78 , C12Q1/00 , H01L51/00 , H01L29/66
CPC classification number: G01N33/5438 , C12Q1/006 , G01N27/414 , G01N27/4145 , G01N27/4148 , H01L29/66484 , H01L29/7831 , H01L29/7832 , H01L51/0093 , H01L51/0512
Abstract: Dual-gate ion-sensitive field effect transistors (ISFETs) for disease diagnostics are disclosed herein. An exemplary dual-gate ISFET includes a gate structure and a fluidic gate structure disposed over opposite surfaces of a device substrate. The gate structure is disposed over a channel region defined between a source region and a drain region in the device substrate. The fluidic gate structure includes a sensing well that is disposed over the channel region. The sensing well includes a sensing layer and an electrolyte solution. The electrolyte solution includes a constituent that can react with a product of an enzymatic reaction that occurs when an enzyme-modified detection mechanism detects an analyte. The sensing layer can react with a first ion generated from the enzymatic reaction and a second ion generated from a reaction between the product of the enzymatic reaction and the constituent, such that the dual-gate ISFET generates an enhanced electrical signal.
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