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    Memory device
    65.
    发明授权
    Memory device 有权

    公开(公告)号：US11508436B2

    公开(公告)日：2022-11-22

    申请号：US17037492

    申请日：2020-09-29

    Applicant: Sharp Semiconductor Innovation Corporation ,  TOHOKU UNIVERSITY

    Inventor： Yoshihisa Sekiguchi ,  Tetsuo Endoh

    IPC: G11C11/16 ,  G11C13/00

    Abstract: A memory device includes: a cell array that includes a first region including first memory cells and a second region including second memory cells; first word lines connected to each of the first memory cells; second word lines connected to each of the second memory cells; a first bit line commonly connected to the first memory cells and the second memory cells; a row decoder that selects one of the first word lines and one of the second word lines in parallel during a data read operation; and a sense amplifier between the first region and the second region and electrically connected to the first bit line during the data read operation.

    Magnetoresistance effect element, magnetic memory array, magnetic memory device, and write method for magnetoresistance effect element
    67.
    发明授权
    Magnetoresistance effect element, magnetic memory array, magnetic memory device, and write method for magnetoresistance effect element 有权

    公开(公告)号：US11430498B2

    公开(公告)日：2022-08-30

    申请号：US17052749

    申请日：2019-04-10

    Applicant: TOHOKU UNIVERSITY

    Inventor： Yoshiaki Saito ,  Shoji Ikeda ,  Tetsuo Endoh

    IPC: G11C11/00 ,  G11C11/16 ,  H01L27/22 ,  H01L43/02

    Abstract: The present invention provides a magnetoresistance effect element with a high read operation speed, a magnetic memory array, a magnetic memory device, and a write method for a magnetoresistance effect element. A magnetoresistance effect element includes: a heavy metal layer; a magnetic recording unit including a recording layer that includes a ferromagnetic layer that is magnetized in a vertical direction with respect to a film surface and is provided on a front surface of the heavy metal layer, a barrier layer that is provided on a surface of the recording layer which is opposite to the heavy metal layer and is formed from an insulator, and a reference layer which is provided on a surface of the barrier layer which is opposite to the recording layer, and a magnetization of the reference layer is fixed in the vertical direction with respect to a film surface; an insulating layer that is provided on a surface of the heavy metal layer which is opposite to the magnetic recording unit; a first terminal that is connected to the insulating layer at a position facing the recording layer with the heavy metal layer and the insulating layer interposed therebetween and applies a voltage to the heavy metal layer through the insulating layer; a second terminal that is connected to the reference layer; and a third terminal and a fourth terminal which are connected to the heavy metal layer, and cause a write current to flow to the heavy metal layer between the magnetic recording unit and the insulating layer.

    Integrated circuit device
    68.
    发明授权
    Integrated circuit device 有权

    公开(公告)号：US11417378B2

    公开(公告)日：2022-08-16

    申请号：US17043257

    申请日：2019-03-12

    Applicant: TOHOKU UNIVERSITY

    Inventor： Tetsuo Endoh ,  Shoji Ikeda ,  Hiroki Koike

    IPC: G11C11/16 ,  G11C13/00 ,  H01L43/02

    Abstract: An integrated circuit device of the invention, includes: a first resistance variable memory element provided on a semiconductor substrate; a second resistance variable memory element provided on the semiconductor substrate; and a semiconductor circuit for controlling write and read of the first resistance variable memory element and the second resistance variable memory element, which is provided on the semiconductor substrate, in which the second resistance variable memory element has a write current that is smaller than a write current of the first resistance variable memory element, and the second resistance variable memory element is disposed farther from the semiconductor substrate than the first resistance variable memory element.

    NONVOLATILE LOGIC CIRCUIT
    70.
    发明申请
    NONVOLATILE LOGIC CIRCUIT 有权

    公开(公告)号：US20220076722A1

    公开(公告)日：2022-03-10

    申请号：US17417917

    申请日：2019-11-28

    Applicant: TOHOKU UNIVERSITY

    Inventor： Masanori Natsui ,  Takahiro Hanyu ,  Tetsuo Endoh

    IPC: G11C11/16 ,  H01L43/02 ,  H01L27/22 ,  H03K19/18

    Abstract: A nonvolatile logic circuit includes: a memory unit having a pair of resistive memory elements; a computation unit connected to the memory unit and configured to perform an operation based on an input signal and a logic value corresponding to a resistance state of the pair of resistive memory elements; a determination circuit configured to determine whether the resistance state of the pair of resistive memory elements is a complementary state or a non-complementary state; and an output circuit connected to the computation unit and the determination circuit, and configured to output a signal corresponding to an operation result by the computation unit or a signal corresponding to a determination result by the determination circuit.

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