公开(公告)号：US11670692B2

公开(公告)日：2023-06-06

申请号：US17218503

申请日：2021-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Wei Hsu ,  Lung-Kun Chu ,  Mao-Lin Huang ,  Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L29/786 ,  H01L29/423 ,  H01L21/8234

CPC classification number: H01L29/41733 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/42392 ,  H01L29/78696

Abstract: A semiconductor device includes power rails in a first interconnect structure on a backside of the semiconductor device. The semiconductor device further includes a gate-all-around (GAA) transistor having multiple channel layers stacked over the first interconnect structure, a gate stack wrapping around each of the multiple channel layers except a bottommost one of the multiple channel layers, and a source/drain feature adjoining the channel layers. The semiconductor device further includes a first conductive via connecting the first interconnect structure to a bottom of the source/drain feature and a dielectric feature isolating the bottommost one of the multiple channel layers from the first conductive via.

公开(公告)号：US11670691B2

公开(公告)日：2023-06-06

申请号：US17504259

申请日：2021-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L21/28 ,  H01L21/8234

CPC classification number: H01L29/41725 ,  H01L21/28097 ,  H01L21/28158 ,  H01L21/823475

Abstract: A device includes a substrate, a gate structure over the substrate, a gate spacer on a sidewall of the gate structure, a source/drain (S/D) region adjacent to the gate spacer, a silicide on the S/D region, a dielectric liner over a sidewall of the gate spacer, wherein a bottom surface of the dielectric liner is spaced away from the silicide by a gap, and an S/D contact over the silicide and at least partially filling the gap.

公开(公告)号：US11621352B2

公开(公告)日：2023-04-04

申请号：US17201812

申请日：2021-03-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Chuan You ,  Chia-Hao Chang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L21/28 ,  H01L21/321 ,  H01L21/768 ,  H01L29/417 ,  H01L29/51

Abstract: A method comprises forming a gate structure over a substrate; forming a gate helmet to cap the gate structure; forming a source/drain contact on the substrate; depositing a contact etch stop layer (CESL) over the gate helmet and the source/drain contacts, and an interlayer dielectric (ILD) layer over the CESL; performing a first etching process to form a gate contact opening extending through the ILD layer, the CESL and the gate helmet to the gate structure; forming a metal cap in the gate contact opening; with the metal cap in the gate contact opening, performing a second etching process to form a source/drain via opening extending through the ILD layer, the CESL to the source/drain contact; and after forming the source/drain via opening, forming a gate contact over the metal cap and a source/drain via over the source/drain contact.

公开(公告)号：US11616143B2

公开(公告)日：2023-03-28

申请号：US17005134

申请日：2020-08-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Yuan Chen ,  Huan-Chieh Su ,  Pei-Yu Wang ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

Abstract: Embodiments of the present disclosure provide a method for forming backside metal contacts with reduced Cgd and increased speed. Particularly, source/drain features on the drain side, or source/drain features without backside metal contact, are recessed from the backside to the level of the inner spacer to reduce Cgd. Some embodiments of the present disclosure use a sacrificial liner to protect backside alignment feature during backside processing, thus, preventing shape erosion of metal conducts and improving device performance.

公开(公告)号：US11594614B2

公开(公告)日：2023-02-28

申请号：US16834637

申请日：2020-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Lung-Kun Chu ,  Chung-Wei Hsu ,  Chih-Hao Wang ,  Mao-Lin Huang

IPC: H01L21/82 ,  H01L21/84 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a gate dielectric layer around first channel layers in a p-type gate region and around second channel layers in an n-type gate region. Sacrificial features are formed between the second channel layers in the n-type gate region. A p-type work function layer is formed over the gate dielectric layer in the p-type gate region and the n-type gate region. After removing the p-type work function layer from the n-type gate region, the sacrificial features are removed from between the second channel layers in the n-type gate region. An n-type work function layer is formed over the gate dielectric layer in the n-type gate region. A metal fill layer is formed over the p-type work function layer in the p-type gate region and the n-type work function layer in the n-type gate region.

公开(公告)号：US20230013764A1

公开(公告)日：2023-01-19

申请号：US17683944

申请日：2022-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chao Chou ,  Yi-Hsun Chiu ,  Shang-Wen Chang ,  Ching-Wei Tsai ,  Chih-Hao Wang ,  Min Cao

IPC: H01L23/522 ,  H01L29/06 ,  H01L29/786 ,  H01L21/8234 ,  H01L23/528

Abstract: Semiconductor devices including backside capacitors and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure, the front-side interconnect structure including a front-side conductive line; a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a backside conductive line, the backside conductive line having a line width greater than a line width of the front-side conductive line; and a first capacitor structure coupled to the backside interconnect structure.

公开(公告)号：US11557510B2

公开(公告)日：2023-01-17

申请号：US17088002

申请日：2020-11-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L21/768 ,  H01L21/762 ,  H01L23/528 ,  H01L29/417 ,  H01L29/66 ,  H01L21/311 ,  H01L23/522

Abstract: Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line in a direction parallel to a backside surface of the first dielectric layer.

公开(公告)号：US11532625B2

公开(公告)日：2022-12-20

申请号：US16781485

申请日：2020-02-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Shi Ning Ju ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51 ,  H01L21/308 ,  H01L21/8238 ,  H01L21/28

Abstract: Aspects of the disclosure provide a semiconductor device and a method for forming the semiconductor device. The semiconductor device includes a plurality of nanostructures stacked over a substrate in a vertical direction, a source/drain terminal adjoining the plurality of nanostructures, and a gate structure around the plurality of nanostructures. The gate structure includes a metal cap connecting adjacent two of the plurality of nanostructures and a metal layer partially surrounding the plurality of nanostructures.

公开(公告)号：US11532518B2

公开(公告)日：2022-12-20

申请号：US17178762

申请日：2021-02-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Sheng-Tsung Wang ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L21/033 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/308 ,  H01L21/768

Abstract: A method of forming an integrated circuit structure includes forming a first source/drain contact plug over and electrically coupling to a source/drain region of a transistor, forming a first dielectric hard mask overlapping a gate stack, recessing the first source/drain contact plug to form a first recess, forming a second dielectric hard mask in the first recess, recessing an inter-layer dielectric layer to form a second recess, and forming a third dielectric hard mask in the second recess. The third dielectric hard mask contacts both the first dielectric hard mask and the second dielectric hard mask.

公开(公告)号：US20220367703A1

公开(公告)日：2022-11-17

申请号：US17869163

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Zhi-Chang Lin ,  Shih-Cheng Chen ,  Chih-Hao Wang ,  Pei-Hsun Wang ,  Lo-Heng Chang ,  Jung-Hung Chang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a first semiconductor channel member and a second semiconductor channel member extending between the first and second source/drain features, and a first dielectric feature and a second dielectric feature each including a first dielectric layer and a second dielectric layer different from the first dielectric layer. The first and second dielectric features are sandwiched between the first and second semiconductor channel members.