公开(公告)号：US20240170553A1

公开(公告)日：2024-05-23

申请号：US18401764

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Hou-Yu Chen ,  Kuan-Lun Cheng

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device according to the present disclosure includes a stack of first channel layers, first and second source/drain (S/D) epitaxial features adjacent to opposite sides of at least a portion of the first channel layers, respectively, a stack of second channel layers stacked over the first channel layers, third and fourth S/D epitaxial features adjacent to opposite sides of at least a portion of the second channel layers, respectively, and a dielectric isolation layer disposed under the first and second S/D epitaxial features. A total active channel layer number of the first channel layers is different from a total active channel layer number of the second channel layers. The dielectric isolation layer is in physical contact with at least a bottommost one of the first channel layers.

公开(公告)号：US20240072052A1

公开(公告)日：2024-02-29

申请号：US18151279

申请日：2023-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Yi-Bo Liao ,  Jin Cai

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/8221 ,  H01L21/823814 ,  H01L21/823871

Abstract: In an embodiment, a device includes: a dielectric wall; nanostructures abutting the dielectric wall; a lower source/drain region adjoining a lower subset of the nanostructures; an upper source/drain region adjoining an upper subset of the nanostructures, the upper source/drain region oppositely doped from the lower source/drain region; and a shared source/drain contact contacting the upper source/drain region and the lower source/drain region, the shared source/drain contact extending into the dielectric wall.

公开(公告)号：US20230369504A1

公开(公告)日：2023-11-16

申请号：US18357357

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Yi-Bo Liao ,  Yu-Xuan Huang ,  Pei-Yu Wang ,  Cheng-Ting Chung ,  Ching-Wei Tsai ,  Hou-Yu Chen

IPC: H01L29/786 ,  H01L23/528 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285 ,  H01L29/06 ,  H01L29/417 ,  H01L29/45 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L29/78618 ,  H01L23/5286 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/7848 ,  H01L21/28518 ,  H01L29/0673 ,  H01L29/78696 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66636 ,  H01L29/66742 ,  H01L21/31116 ,  H01L21/02603

Abstract: In an embodiment, a device includes: a first interconnect structure including metallization patterns; a second interconnect structure including a power rail; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor, the first transistor including an epitaxial source/drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization patterns, the conductive via contacting the epitaxial source/drain region.

公开(公告)号：US11532711B2

公开(公告)日：2022-12-20

申请号：US17021765

申请日：2020-09-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Kuan-Lun Cheng

IPC: H01L29/78 ,  H01L29/167 ,  H01L29/165 ,  H01L29/66 ,  H01L29/06

Abstract: A semiconductor device according to the present disclosure includes a first source/drain epitaxial feature and a second source/drain epitaxial feature each having an outer liner layer and an inner filler layer, a plurality of channel members extending between the first source/drain epitaxial feature and the second source/drain epitaxial feature along a first direction, and a gate structure disposed over and around the plurality of channel members. The plurality of channel members are in contact with the outer liner layer and are spaced apart from the inner filler layer. The outer liner layer comprises germanium and boron and the inner filler layer comprises germanium and gallium.

公开(公告)号：US20220393001A1

公开(公告)日：2022-12-08

申请号：US17884636

申请日：2022-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Kuan-Lun Cheng

IPC: H01L29/167 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device according to the present disclosure includes a first source/drain epitaxial feature and a second source/drain epitaxial feature each having an outer liner layer and an inner filler layer, a plurality of channel members extending between the first source/drain epitaxial feature and the second source/drain epitaxial feature along a first direction, and a gate structure disposed over and around the plurality of channel members. The plurality of channel members are in contact with the outer liner layer and are spaced apart from the inner filler layer. The outer liner layer comprises germanium and boron and the inner filler layer comprises germanium and gallium.

公开(公告)号：US20220367454A1

公开(公告)日：2022-11-17

申请号：US17815112

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Hou-Yu Chen ,  Ching-Wei Tsai

IPC: H01L27/088 ,  H01L23/50 ,  H01L27/06 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417

Abstract: Backside interconnect structures having reduced critical dimensions for semiconductor devices and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure over a front-side of a substrate; a first backside interconnect structure over a backside of the substrate, the first backside interconnect structure including first conductive features having tapered sidewalls with widths that narrow in a direction away from the substrate; a power rail extending through the substrate, the power rail being electrically coupled to the first conductive features; and a first source/drain contact extending from the power rail to a first source/drain region of the first transistor structure.

公开(公告)号：US11417766B2

公开(公告)日：2022-08-16

申请号：US17023125

申请日：2020-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/04

Abstract: A semiconductor device according to the present disclosure includes a first transistor and a second transistor. The first transistor includes a plurality of first channel members and a first gate structure wrapping around each of the plurality of first channel members. The second transistor includes a plurality of second channel members and a second gate structure disposed over the plurality of second channel members. Each of the plurality of first channel members has a first width and a first height smaller than the first width. Each of the plurality of second channel members has a second width and a second height greater than the second width.

公开(公告)号：US20210375861A1

公开(公告)日：2021-12-02

申请号：US17026870

申请日：2020-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Hou-Yu Chen ,  Ching-Wei Tsai

IPC: H01L27/088 ,  H01L23/50 ,  H01L27/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762

Abstract: Backside interconnect structures having reduced critical dimensions for semiconductor devices and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure over a front-side of a substrate; a first backside interconnect structure over a backside of the substrate, the first backside interconnect structure including first conductive features having tapered sidewalls with widths that narrow in a direction away from the substrate; a power rail extending through the substrate, the power rail being electrically coupled to the first conductive features; and a first source/drain contact extending from the power rail to a first source/drain region of the first transistor structure.

公开(公告)号：US20210336063A1

公开(公告)日：2021-10-28

申请号：US16998576

申请日：2020-08-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Bo Liao ,  Yu-Xuan Huang ,  Pei-Yu Wang ,  Cheng-Ting Chung ,  Ching-Wei Tsai ,  Hou-Yu Chen

IPC: H01L29/786 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L21/02 ,  H01L21/311 ,  H01L21/285 ,  H01L29/66

Abstract: In an embodiment, a device includes: a first interconnect structure including metallization patterns; a second interconnect structure including a power rail; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor, the first transistor including an epitaxial source/drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization patterns, the conductive via contacting the epitaxial source/drain region.

公开(公告)号：US20210082803A1

公开(公告)日：2021-03-18

申请号：US16572670

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Wang ,  Cheng-Ting Chung ,  Wei Ju Lee

IPC: H01L23/522 ,  H01L21/768

Abstract: Semiconductor devices and method of forming the same are disclosed herein. A semiconductor device according to the present disclosure includes a first dielectric layer having a first top surface and a contact via extending through the first dielectric layer and rising above the first top surface of the first dielectric layer.