公开(公告)号：US12148837B2

公开(公告)日：2024-11-19

申请号：US18357357

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Bo Liao ,  Yu-Xuan Huang ,  Pei-Yu Wang ,  Cheng-Ting Chung ,  Ching-Wei Tsai ,  Hou-Yu Chen

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: In an embodiment, a device includes: a first interconnect structure including metallization patterns; a second interconnect structure including a power rail; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor, the first transistor including an epitaxial source/drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization patterns, the conductive via contacting the epitaxial source/drain region.

公开(公告)号：US20240194787A1

公开(公告)日：2024-06-13

申请号：US18581153

申请日：2024-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/7855 ,  H01L21/823431 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66818 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/045 ,  H01L2029/7858

Abstract: A semiconductor device according to the present disclosure includes a first transistor and a second transistor. The first transistor includes a plurality of first channel members and a first gate structure wrapping around each of the plurality of first channel members. The second transistor includes a plurality of second channel members and a second gate structure disposed over the plurality of second channel members. Each of the plurality of first channel members has a first width and a first height smaller than the first width. Each of the plurality of second channel members has a second width and a second height greater than the second width.

公开(公告)号：US11948989B2

公开(公告)日：2024-04-02

申请号：US17699303

申请日：2022-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Yi-Bo Liao ,  Hou-Yu Chen ,  Kuan-Lun Cheng

IPC: H01L29/423 ,  H01L21/306 ,  H01L21/311 ,  H01L21/321 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/3212 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/401 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate; semiconductor layers over the substrate, wherein the semiconductor layers are separate from each other and are stacked up along a direction generally perpendicular to a top surface of the substrate; a dielectric feature over and separate from the semiconductor layers; and a gate structure wrapping around each of the semiconductor layers, the gate structure having a gate dielectric layer and a gate electrode layer, wherein the gate dielectric layer interposes between the gate electrode layer and the dielectric feature and the dielectric feature is disposed over at least a part of the gate electrode layer.

公开(公告)号：US11908942B2

公开(公告)日：2024-02-20

申请号：US17860022

申请日：2022-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/10 ,  H01L29/786 ,  H01L29/06 ,  H01L29/775 ,  H01L29/04 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/7855 ,  H01L21/823431 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66818 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/045 ,  H01L2029/7858

Abstract: A semiconductor device according to the present disclosure includes a first transistor and a second transistor. The first transistor includes a plurality of first channel members and a first gate structure wrapping around each of the plurality of first channel members. The second transistor includes a plurality of second channel members and a second gate structure disposed over the plurality of second channel members. Each of the plurality of first channel members has a first width and a first height smaller than the first width. Each of the plurality of second channel members has a second width and a second height greater than the second width.

公开(公告)号：US20230378363A1

公开(公告)日：2023-11-23

申请号：US18361491

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Hsun Wang ,  Chun-Hsiung Lin ,  Cheng-Ting Chung ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/823431 ,  H01L29/0665 ,  H01L29/66795 ,  H01L29/0653 ,  H01L21/823412 ,  H01L21/823418

Abstract: A semiconductor device according to the present disclosure includes a first isolation feature and a second isolation feature, a fin structure extending lengthwise along a first direction and sandwiched between the first isolation feature and the second isolation feature along a second direction perpendicular to the first direction, a first channel member disposed over the first isolation feature, a second channel member disposed over the second isolation feature, and a gate structure disposed over and wrapping around the first channel member and the second channel member.

公开(公告)号：US20220375860A1

公开(公告)日：2022-11-24

申请号：US17815119

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Xuan Huang ,  Ching-Wei Tsai ,  Cheng-Ting Chung ,  Cheng-Chi Chuang ,  Shang-Wen Chang

IPC: H01L23/528 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a substrate having a front side and a back side; a gate stack formed on the front side of the substrate and disposed on an active region of the substrate; a first source/drain feature formed on the active region and disposed at an edge of the gate stack; a backside power rail formed on the back side of the substrate; and a backside contact feature interposed between the backside power rail and the first source/drain feature, and electrically connecting the backside power rail to the first source/drain feature. The backside contact feature further includes a first silicide layer on the back side of the substrate and directly contacting a bottom surface of the first source/drain feature.

公开(公告)号：US20220352377A1

公开(公告)日：2022-11-03

申请号：US17860022

申请日：2022-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10 ,  H01L21/8234 ,  H01L29/786 ,  H01L29/06 ,  H01L29/775

Abstract: A semiconductor device according to the present disclosure includes a first transistor and a second transistor. The first transistor includes a plurality of first channel members and a first gate structure wrapping around each of the plurality of first channel members. The second transistor includes a plurality of second channel members and a second gate structure disposed over the plurality of second channel members. Each of the plurality of first channel members has a first width and a first height smaller than the first width. Each of the plurality of second channel members has a second width and a second height greater than the second width.

公开(公告)号：US11217484B2

公开(公告)日：2022-01-04

申请号：US16449014

申请日：2019-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L21/82 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088

Abstract: A method for fabricating a semiconductor device having a dielectric footing region includes forming a plurality of fin elements extending from a substrate. In some embodiments, a dielectric layer is deposited over each of the plurality of fin elements. After depositing the dielectric layer, a dummy gate electrode is formed over the plurality of fin elements and over the dielectric layer. In some examples, and after forming the dummy gate electrode, a first spacer layer is formed on opposing sidewalls of the dummy gate electrode and over the dielectric layer. In various embodiments, the dielectric layer extends laterally beneath the first spacer layer on each of the opposing sidewalls of the dummy gate electrode to provide the dielectric footing region.

公开(公告)号：US20210265349A1

公开(公告)日：2021-08-26

申请号：US16802311

申请日：2020-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306

Abstract: A semiconductor device according to the present disclosure includes a first plurality of gate-all-around (GAA) devices in a first device area and a second plurality of GAA devices in a second device area. Each of the first plurality of GAA devices includes a first vertical stack of channel members extending along a first direction, and a first gate structure over and around the first vertical stack of channel members. Each of the second plurality of GAA devices includes a second vertical stack of channel members extending along a second direction, and a second gate structure over and around the second vertical stack of channel members. Each of the first plurality of GAA devices includes a first channel length and each of the second plurality of GAA devices includes a second channel length smaller than the first channel length.

公开(公告)号：US20210134718A1

公开(公告)日：2021-05-06

申请号：US16832833

申请日：2020-03-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Bo LIAO ,  Wei Ju Lee ,  Cheng-Ting Chung ,  Hou-Yu Chen ,  Chun-Fu Cheng ,  Kuan-Lun Cheng

IPC: H01L23/522 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L23/528

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and a conductive rail structure between the first and second vertical structures. A top surface of the conductive rail structure can be substantially coplanar with top surfaces of the first and the second vertical structures.