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    Semiconductor device structure and methods of forming the same
    62.
    发明授权
    Semiconductor device structure and methods of forming the same 有权

    公开(公告)号：US11355398B2

    公开(公告)日：2022-06-07

    申请号：US17027282

    申请日：2020-09-21

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Kuan-Ting Pan ,  Kuo-Cheng Chiang ,  Shang-Wen Chang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/768

    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first and second gate electrode layers, and a dielectric feature disposed between the first and second gate electrode layers. The dielectric feature has a first surface. The structure further includes a first conductive layer disposed on the first gate electrode layer. The first conductive layer has a second surface. The structure further includes a second conductive layer disposed on the second electrode layer. The second conductive layer has a third surface, and the first, second, and third surfaces are coplanar. The structure further includes a third conductive layer disposed over the first conductive layer, a fourth conductive layer disposed over the second conductive layer, and a dielectric layer disposed on the first surface of the dielectric feature. The dielectric layer is disposed between the third conductive layer and the fourth conductive layer.

    Self-Aligned Metal Gate for Multigate Device
    66.
    发明申请
    Self-Aligned Metal Gate for Multigate Device 有权

    公开(公告)号：US20210343600A1

    公开(公告)日：2021-11-04

    申请号：US17174109

    申请日：2021-02-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Guan-Lin Chen ,  Kuo-Cheng Chiang ,  Chih-Hao Wang ,  Kuan-Lun Cheng ,  Ching-Wei Tsai ,  Shi Ning Ju ,  Jui-Chien Huang

    IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

    Abstract: Self-aligned gate cutting techniques for multigate devices are disclosed herein that provide multigate devices having asymmetric metal gate profiles and asymmetric source/drain feature profiles. An exemplary multigate device has a channel layer, a metal gate that wraps a portion of the channel layer, and source/drain features disposed over a substrate. The channel layer extends along a first direction between the source/drain features. A first dielectric fin and a second dielectric fin are disposed over the substrate and configured differently. The channel layer extends along a second direction between the first dielectric fin and the second dielectric fin. The metal gate is disposed between the channel layer and the second dielectric fin. In some embodiments, the first dielectric fin is disposed on a first isolation feature, and the second dielectric fin is disposed on a second isolation feature. The first isolation feature and the second isolation feature are configured differently.

    Self-Aligned Etch in Semiconductor Devices
    68.
    发明申请
    Self-Aligned Etch in Semiconductor Devices 有权

    公开(公告)号：US20210335783A1

    公开(公告)日：2021-10-28

    申请号：US16944025

    申请日：2020-07-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yi-Hsun Chiu ,  Ching-Wei Tsai ,  Yu-Xuan Huang ,  Cheng-Chi Chuang ,  Shang-Wen Chang

    IPC: H01L27/088 ,  H01L29/78 ,  H01L29/423 ,  H01L23/535 ,  H01L29/417 ,  H01L29/66 ,  H01L21/768

    Abstract: Methods of performing backside etching processes on source/drain regions and gate structures of semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a first interconnect structure on a front-side of the first transistor structure; and a second interconnect structure on a backside of the first transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and first spacers along sidewalls of the contact between the contact and the first dielectric layer, sidewalls of the first spacers facing the first dielectric layer being aligned with sidewalls of the source/drain region of the first transistor structure.

    Structure and method for gate-all-around device with extended channel
    69.
    发明授权
    Structure and method for gate-all-around device with extended channel 有权

    公开(公告)号：US11158727B2

    公开(公告)日：2021-10-26

    申请号：US16509184

    申请日：2019-07-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Pei-Hsun Wang ,  Chih-Chao Chou ,  Chun-Hsiung Lin ,  Ching-Wei Tsai ,  Chih-Hao Wang

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/40 ,  H01L29/06

    Abstract: The present disclosure provides a method of semiconductor fabrication that includes forming a semiconductor fin protruding from a substrate, the semiconductor fin including a plurality of first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked, the second semiconductor material being different from the first semiconductor material in composition; forming a first gate stack on the semiconductor fin; forming a recess in the semiconductor fin within a source/drain (S/D) region adjacent to the first gate stack, a sidewall of the first and second semiconductor material layers being exposed within the recess; performing an etching process to the semiconductor fin, resulting in an undercut below the first gate stack; epitaxially growing on the sidewall of the semiconductor fin to fill in the undercut with a semiconductor extended feature of the first semiconductor material; and growing an epitaxial S/D feature from the recess.

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