公开(公告)号：US20220367666A1

公开(公告)日：2022-11-17

申请号：US17873825

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Marcus Johannes Henricus van Dal ,  Gerben Doornbos ,  Georgios Vellianitis

IPC: H01L29/51 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first gate electrode, a ferroelectric insulating layer over the first gate electrode, a semiconductor member over the ferroelectric insulating layer, a gate dielectric layer over the semiconductor member, and a second gate electrode over the gate dielectric layer.

公开(公告)号：US11411103B2

公开(公告)日：2022-08-09

申请号：US15930285

申请日：2020-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Timothy Vasen ,  Gerben Doornbos ,  Matthias Passlack

IPC: H01L29/06 ,  H01L29/775 ,  H01L29/205 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08

Abstract: The current disclosure describes a tunnel FET device including a P-I-N heterojunction structure. A high-K dielectric layer and a metal gate wrap around the intrinsic channel layer with an interlayer positioned between high-K dielectric layer and the intrinsic channel layer of the P-I-N heterojunction. The interlayer prevents charge carriers from reaching the interface with high-K dielectric layer under the trap-assisted tunneling effect and reduces OFF state leakage.

公开(公告)号：US11257818B2

公开(公告)日：2022-02-22

申请号：US16353664

申请日：2019-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Matthias Passlack ,  Gerben Doornbos ,  Peter Ramvall

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/308 ,  H01L29/20 ,  H01L29/78 ,  H01L29/51 ,  H01L21/8238 ,  H01L29/66

Abstract: The present disclosure describes a semiconductor structure that includes a substrate from an undoped semiconductor material and a fin disposed on the substrate. The fin includes a non-polar top surface and two opposing first and second polar sidewall surfaces. The semiconductor structure further includes a polarization layer on the first polar sidewall surface, a doped semiconductor layer on the polarization layer, a dielectric layer on the doped semiconductor layer and on the second polar sidewall surface, and a gate electrode layer on the dielectric layer and the first polarized sidewall surface.

公开(公告)号：US20220020919A1

公开(公告)日：2022-01-20

申请号：US16933914

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Georgios Vellianitis ,  Gerben Doornbos ,  Marcus Johannes Henricus Van Dal ,  Mauricio MANFRINI

IPC: H01L43/04 ,  H01L43/06 ,  H01L27/22 ,  H01L43/10 ,  H01L43/14

Abstract: A semiconductor device includes a storage element layer and a selector. The selector is electrically coupled to the storage element layer, and includes a first insulating layer, a second insulating layer, a third insulating layer, a first conductive layer and a second conductive layer. The first insulating layer, the second insulating layer and the third insulating layer are stacked up in sequence, wherein the second insulating layer is sandwiched in between the first insulating layer and the third insulating layer, and the first insulating layer and the third insulating layer include materials with higher band gap as compared with a material of the second insulating layer. The first conductive layer is connected to the first insulting layer, and the second conductive layer is connected to the third insulating layer.

公开(公告)号：US20210225647A1

公开(公告)日：2021-07-22

申请号：US17224981

申请日：2021-04-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Matthias Passlack ,  Blandine Duriez ,  Georgios Vellianitis ,  Gerben Doornbos ,  Marcus Johannes Henricus Van Dal ,  Martin Christopher Holland ,  Mauricio Manfrini

IPC: H01L21/02 ,  H01L29/786 ,  H01L29/66

Abstract: A crystalline channel layer of a semiconductor material is formed in a backend process over a crystalline dielectric seed layer. A crystalline magnesium oxide MgO is formed over an amorphous inter-layer dielectric layer. The crystalline MgO provides physical link to the formation of a crystalline semiconductor layer thereover.

公开(公告)号：US11024548B2

公开(公告)日：2021-06-01

申请号：US16201328

申请日：2018-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mark Van Dal ,  Gerben Doornbos

IPC: H01L21/8238 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L27/092 ,  H01L29/78 ,  H01L21/822 ,  H01L27/06 ,  H01L27/11

Abstract: A fin including a bottom portion, a first sacrificial layer disposed over the bottom portion, a first semiconductor layer disposed over the first sacrificial layer, a second sacrificial layer disposed over the first semiconductor layer and a second semiconductor layer disposed over the second sacrificial layer, is formed. The second semiconductor layer protrudes from a first insulating layer. A dummy gate is formed over the second semiconductor layer. A sidewall spacer layer is formed on side faces of the dummy gate. A first dielectric layer is formed over the dummy gate and the sidewall spacer layer. The dummy gate is removed, thereby forming a gate space. The first insulating layer is etched in the gate space, thereby exposing the first semiconductor layer and the first and second sacrificial layers. The first and second sacrificial layers are removed. A gate dielectric layer and a gate electrode layer are formed.

公开(公告)号：US10991576B2

公开(公告)日：2021-04-27

申请号：US16585571

申请日：2019-09-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Matthias Passlack ,  Blandine Duriez ,  Georgios Vellianitis ,  Gerben Doornbos ,  Marcus Johannes Henricus Van Dal ,  Martin Christopher Holland ,  Mauricio Manfrini

IPC: H01L21/02 ,  H01L29/786 ,  H01L29/66

Abstract: A crystalline channel layer of a semiconductor material is formed in a backend process over a crystalline dielectric seed layer. A crystalline magnesium oxide MgO is formed over an amorphous inter-layer dielectric layer. The crystalline MgO provides physical link to the formation of a crystalline semiconductor layer thereover.

公开(公告)号：US20210098633A1

公开(公告)日：2021-04-01

申请号：US16588453

申请日：2019-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Blandine Duriez ,  Marcus Johannes Henricus Van Dal ,  Martin Christopher Holland ,  Gerben Doornbos ,  Georgios Vellianitis

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L21/311 ,  H01L21/268 ,  H01L21/285 ,  H01L21/324 ,  H01L29/66

Abstract: A method of forming a semiconductor device includes forming source/drain contact openings extending through at least one dielectric layer to expose source/drain contact regions of source/drain structures. The method further includes forming conductive plugs in the source/drain contact openings. The method further includes depositing a light blocking layer over the conductive plugs and the at least one dielectric layer. The method further includes etching the light blocking layer to expose the conductive plugs. The method further includes directing a laser irradiation to the conductive plugs and the light blocking layer. The laser irradiation is configured to activate dopants in the source/drain contact regions.

公开(公告)号：US10923581B2

公开(公告)日：2021-02-16

申请号：US16695650

申请日：2019-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gerben Doornbos ,  Peter Ramvall ,  Matthias Passlack ,  Carlos H. Diaz

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/092 ,  H01L29/786 ,  H01L21/306 ,  H01L21/02 ,  H01L21/8252 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor structure including forming a first type semiconductor layer. The method also includes forming a semiconductor interlayer over the first type semiconductor layer. The method further includes forming a second type semiconductor layer over the semiconductor interlayer. The method further includes etching the first type semiconductor layer, the semiconductor interlayer, and the second type semiconductor layer to form a fin structure. The method further includes oxidizing the semiconductor interlayer.

公开(公告)号：US20210043839A1

公开(公告)日：2021-02-11

申请号：US17068736

申请日：2020-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Timothy Vasen ,  Marcus Johannes Henricus Van Dal ,  Gerben Doornbos ,  Matthias Passlack

IPC: H01L51/00 ,  C23C16/455 ,  C23C16/56 ,  H01L23/544

Abstract: Provided herein are wafers that can be used to align carbon nanotubes, as well as methods of making and using the same. Such wafers include alignment areas that have four sides and a surface charge, where the alignment areas are surrounded by areas that have a surface charge of a different polarity. Methods of the disclosure may include depositing and selectively etching a number of hardmasks on a substrate. The described methods may also include depositing a carbon nanotube on such a wafer.