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67 条记录 (耗时 0.024 秒)

    Power switch control for dual power supply
    62.
    发明授权
    Power switch control for dual power supply 有权

    公开(公告)号：US10304500B2

    公开(公告)日：2019-05-28

    申请号：US15902118

    申请日：2018-02-22

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Fu-An Wu ,  Cheng Hung Lee ,  Chen-Lin Yang ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang ,  Yu-Hao Hsu

    IPC分类号： G11C5/14 ,  H03K17/687 ,  H03K17/22

    摘要： An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.

    Level shifter circuit using boosting circuit
    64.
    发明授权
    Level shifter circuit using boosting circuit 有权

    公开(公告)号：US09762216B1

    公开(公告)日：2017-09-12

    申请号：US15065166

    申请日：2016-03-09

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Mahmut Sinangil ,  Hsin-Hsin Ko ,  Chiting Cheng ,  Yen-Huei Chen ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang

    IPC分类号： H03L5/00 ,  H03K3/356 ,  H03K19/0185

    CPC分类号： H03K3/356113 ,  H03K19/018521

    摘要： A level shifter circuit is provided that uses a boosting circuit. The boosting circuit is configured to improve the operation of the level shifter circuit when the high voltages of voltage domains across the level shifter circuit are widely separated. A circuit apparatus includes a core level shifter circuit that changes a first voltage of an input signal to a second voltage of an output signal. The circuit apparatus further includes a first boosting circuit that is coupled to the core level shifter circuit and generates a first transient voltage applied to the core level shifter circuit when the input signal transitions from a low value to a high value. The circuit apparatus also includes a second boosting circuit that is coupled to the core level shifter circuit and generates a second transient voltage applied to the core level shifter circuit when the input signal transitions from a high value to a low value.

    Pre-colored methodology of multiple patterning
    66.
    发明授权
    Pre-colored methodology of multiple patterning 有权
    多色图案的预色方法

    公开(公告)号：US09183341B2

    公开(公告)日：2015-11-10

    申请号：US14218001

    申请日：2014-03-18

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Yen-Huei Chen ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072 ,  G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    摘要： Some embodiments relate to a system that pre-colors word lines and control lines within a memory cell to avoid timing delays that result from processing variations introduced through multiple patterning lithography processes. The system has a memory element that stores a graphical IC layout with a memory circuit having layout features including a plurality of word lines and a plurality of Y-control lines. A pre-coloring element pre-colors one or more of the plurality of word lines and Y-control lines, to indicate that pre-colored word lines and Y-control lines are to be formed on a same mask of a multiple mask set used for a multiple patterning lithography process. A decomposition element assigns different colors to uncolored layout features of the memory circuit, to indicate that different colored memory features are to be formed on different masks of the multiple mask set.

    摘要翻译： 一些实施例涉及对存储器单元内的字线和控制线进行预色彩以避免由通过多次图案化光刻工艺引入的处理变化而产生的定时延迟的系统。 该系统具有存储图形IC布局的存储元件，其具有包括多个字线和多个Y控制线的布局特征的存储器电路。 预着色元件对多个字线和Y控制线中的一个或多个进行预色，以指示预先着色的字线和Y控制线将被形成在所使用的多个掩模集的相同掩模上 用于多重图案化光刻工艺。 分解元素将不同的颜色分配给存储器电路的未着色布局特征，以指示将在多个掩模集合的不同掩模上形成不同的彩色存储器特征。

    Power line lowering for write assisted control scheme
    67.
    发明授权
    Power line lowering for write assisted control scheme 有权
    写辅助控制方案的电源线降低

    公开(公告)号：US09093176B2

    公开(公告)日：2015-07-28

    申请号：US13674192

    申请日：2012-11-12

    申请人： Taiwan Semiconductor Manufacturing Co. Ltd.

    发明人： Wei-Cheng Wu ,  Wei Min Chan ,  Yen-Huei Chen ,  Hung-Jen Liao

    IPC分类号： G11C11/419 ,  G11C11/4197

    CPC分类号： G11C11/419

    摘要： Some embodiments of the present disclosure relate to a memory array having a cell voltage generator configured to provide a cell voltage header to a plurality of memory cells. The cell voltage generator is connected to the memory cells by way of supply voltage line and controls a supply voltage of the memory cells. The cell voltage generator has a pull-down element coupled between a control node of the supply voltage line and a ground terminal, and a one or more pull-up elements connected in parallel between the control node and a cell voltage source. A control unit is configured to provide one or more variable valued pull-up enable signals to input nodes of the pull-up elements. The variable valued pull-up enable signals operate the pull-up elements to selectively connect the supply voltage line from the cell voltage source to provide a cell voltage header with a high slew rate.

    摘要翻译： 本公开的一些实施例涉及具有单元电压发生器的存储器阵列，其被配置为向多个存储器单元提供单元电压报头。 电池电压发生器通过电源电压线连接到存储器单元，并控制存储器单元的电源电压。 电池电压发生器具有耦合在电源电压线的控制节点和接地端子之间的下拉元件以及在控制节点和电池电压源之间并联连接的一个或多个上拉元件。 控制单元被配置为向上拉元件的输入节点提供一个或多个可变值上拉使能信号。 可变值上拉使能信号操作上拉元件以选择性地将电源电压线与电池电压源连接，以提供具有高压摆率的电池电压头。