公开(公告)号：US10658468B2

公开(公告)日：2020-05-19

申请号：US16206500

申请日：2018-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tetsuji Ueno ,  Ming-Hua Yu ,  Chan-Lon Yang

IPC: H01L21/00 ,  H01L29/167 ,  H01L21/02 ,  C23C16/02 ,  C30B25/18 ,  C30B29/06 ,  C23C16/44 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78

Abstract: A method and structure for providing a two-step defect reduction bake, followed by a high-temperature epitaxial layer growth. In various embodiments, a semiconductor wafer is loaded into a processing chamber. While the semiconductor wafer is loaded within the processing chamber, a first pre-epitaxial layer deposition baking process is performed at a first pressure and first temperature. In some cases, after the first pre-epitaxial layer deposition baking process, a second pre-epitaxial layer deposition baking process is then performed at a second pressure and second temperature. In some embodiments, the second pressure is different than the first pressure. By way of example, after the second pre-epitaxial layer deposition baking process and while at a growth temperature, a precursor gas may then be introduced into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.

公开(公告)号：US10516037B2

公开(公告)日：2019-12-24

申请号：US15801097

申请日：2017-11-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Jing Lee ,  Ming-Hua Yu

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/04 ,  H01L27/092

Abstract: In a method for manufacturing a semiconductor device, an isolation insulating layer is formed over a fin structure. A first portion of the fin structure is exposed from and a second portion of the fin structure is embedded in the isolation insulating layer. A dielectric layer is formed over sidewalls of the first portion of the fin structure. The first portion of the fin structure and a part of the second portion of the fin structure in a source/drain region are removed, thereby forming a trench. A source/drain epitaxial structure is formed in the trench using one of a first process or a second process. The first process comprises an enhanced epitaxial growth process having an enhanced growth rate for a preferred crystallographic facet, and the second process comprises using a modified etch process to reduce a width of the source/drain epitaxial structure.

公开(公告)号：US10510753B2

公开(公告)日：2019-12-17

申请号：US15895987

申请日：2018-02-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Jing Lee ,  Kun-Mu Li ,  Ming-Hua Yu ,  Tsz-Mei Kwok

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06

Abstract: An integrated circuit includes first and second semiconductor fins, first and second epitaxy structures, and first and second dielectric fin sidewall structures. The first and second epitaxy structures are respectively on the first and second semiconductor fins. The first epitaxy structure and the second epitaxy structure are merged together. The first and second dielectric fin sidewall structures are respectively on opposite first and second sidewalls of the first epitaxy structure. The first sidewall of the first epitaxy structure faces the second epitaxy structure. The first dielectric fin sidewall structure is shorter than the second dielectric fin sidewall structure.

公开(公告)号：US10170483B2

公开(公告)日：2019-01-01

申请号：US15702569

申请日：2017-09-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Jing Lee ,  Tsz-Mei Kwok ,  Ming-Hua Yu ,  Kun-Mu Li

IPC: H01L27/11 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L27/02

Abstract: A semiconductor device includes a substrate, a first semiconductor fin, a second semiconductor fin, an n-type epitaxy structure, a p-type epitaxy structure, and a plurality of dielectric fin sidewall structures. The first semiconductor fin is disposed on the substrate. The second semiconductor fin is disposed on the substrate and adjacent to the first semiconductor fin. The n-type epitaxy structure is disposed on the first semiconductor fin. The p-type epitaxy structure is disposed on the second semiconductor fin and separated from the n-type epitaxy structure. The dielectric fin sidewall structures are disposed on opposite sides of at least one of the n-type epitaxy structure and the p-type epitaxy structure.

公开(公告)号：US20180350687A1

公开(公告)日：2018-12-06

申请号：US16049971

申请日：2018-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Jing Lee ,  Jeng-Wei Yu ,  Li-Wei Chou ,  Tsz-Mei Kwok ,  Ming-Hua Yu

IPC: H01L21/822 ,  H01L27/092 ,  H01L27/088 ,  H01L27/06 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/84

Abstract: A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a substrate, two semiconductor fins over the substrate, and a semiconductor feature over the two semiconductor fins. The semiconductor feature comprises two lower portions and one upper portion. The two lower portions are directly over the two semiconductor fins respectively. The upper portion is over the two lower portions. A bottom surface of the upper portion has an arc-like cross-sectional shape.

公开(公告)号：US09922975B2

公开(公告)日：2018-03-20

申请号：US14875504

申请日：2015-10-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Jing Lee ,  Kun-Mu Li ,  Ming-Hua Yu ,  Tsz-Mei Kwok

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/0649

Abstract: An integrated circuit includes a first semiconductor fin, a first epitaxy structure, and at least two first dielectric fin sidewall structures. The first epitaxy structure is disposed on the first semiconductor fin. The first dielectric fin sidewall structures are disposed on opposite sidewalls of the first epitaxy structure. The first dielectric fin sidewall structures have different heights.

公开(公告)号：US20170221709A1

公开(公告)日：2017-08-03

申请号：US15089153

申请日：2016-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tetsuji Ueno ,  Ming-Hua Yu ,  Chan-Lon Yang

IPC: H01L21/02 ,  H01L29/167

Abstract: A method and structure for providing a two-step defect reduction bake, followed by a high-temperature epitaxial layer growth. In various embodiments, a semiconductor wafer is loaded into a processing chamber. While the semiconductor wafer is loaded within the processing chamber, a first pre-epitaxial layer deposition baking process is performed at a first pressure and first temperature. In some cases, after the first pre-epitaxial layer deposition baking process, a second pre-epitaxial layer deposition baking process is then performed at a second pressure and second temperature. In some embodiments, the second pressure is different than the first pressure. By way of example, after the second pre-epitaxial layer deposition baking process and while at a growth temperature, a precursor gas may then be introduced into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.

公开(公告)号：US09502561B1

公开(公告)日：2016-11-22

申请号：US14925670

申请日：2015-10-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Chiang Chang ,  Hsueh-Chang Sung ,  Kun-Mu Li ,  Ming-Hua Yu

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/161 ,  H01L29/16 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

Abstract: An embodiment is a semiconductor device, comprising: a substrate; a plurality of fin structures disposed on the substrate; a plurality of first strained materials disposed on each of the plurality of the fin structures; a plurality of cap layers individually formed on each of the plurality of first strained materials, wherein at least two cap layers are connected to each other; a second strained material disposed on the at least two cap layers which are connected to each other.

Abstract translation: 一个实施例是半导体器件，包括：衬底; 设置在所述基板上的多个翅片结构; 设置在所述多个翅片结构中的每一个上的多个第一应变材料; 多个盖层分别形成在所述多个第一应变材料中的每一个上，其中至少两个盖层彼此连接; 设置在彼此连接的至少两个盖层上的第二应变材料。

公开(公告)号：US12154974B2

公开(公告)日：2024-11-26

申请号：US18521556

申请日：2023-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chiang Chang ,  Ming-Hua Yu ,  Li-Li Su

IPC: H01L29/66 ,  H01L21/20 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/417 ,  H01L29/78

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in an n-type Fin Field-Effect (FinFET) region and a p-type FinFET region, respectively, forming a first dielectric fin and a second dielectric fin in the n-type FinFET region and the p-type FinFET region, respectively, forming a first epitaxy mask to cover the second semiconductor fin and the second dielectric fin, performing a first epitaxy process to form an n-type epitaxy region based on the first semiconductor fin, removing the first epitaxy mask, forming a second epitaxy mask to cover the n-type epitaxy region and the first dielectric fin, performing a second epitaxy process to form a p-type epitaxy region based on the second semiconductor fin, and removing the second epitaxy mask. After the second epitaxy mask is removed, a portion of the second epitaxy mask is left on the first dielectric fin.

公开(公告)号：US20240355910A1

公开(公告)日：2024-10-24

申请号：US18760829

申请日：2024-07-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Jing Lee ,  Ming-Hua Yu

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/08 ,  H01L29/167 ,  H01L29/36 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7851 ,  H01L21/28088 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/4966

Abstract: A method includes recessing a semiconductor fin to form a recess, wherein the semiconductor fin protrudes higher than isolation regions on opposite sides of the semiconductor fin, and performing a first epitaxy to grow a first epitaxy layer extending into the recess. The first epitaxy is performed using a first process gas comprising a silicon-containing gas, silane, and a phosphorous-containing gas. The first epitaxy layer has a first phosphorous atomic percentage. The method further includes performing a second epitaxy to grow a second epitaxy layer extending into the recess and over the first epitaxy layer. The second epitaxy is performed using a second process gas comprising the silicon-containing gas, silane, and the phosphorous-containing gas. The second epitaxy layer has a second phosphorous atomic percentage higher than the first phosphorous atomic percentage.