公开(公告)号：US12057449B2

公开(公告)日：2024-08-06

申请号：US17816044

申请日：2022-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Shuo Chen ,  Chia-Der Chang ,  Yi-Jing Lee

IPC: H01L27/088 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8234 ,  H01L27/092

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0924 ,  H01L21/31116 ,  H01L21/32135 ,  H01L27/0928

Abstract: A semiconductor device with an isolation structure and a method of fabricating the same are disclosed. The semiconductor device includes first and second fin structures disposed on a substrate and first and second pairs of gate structures disposed on the first and second fin structures. The first end surfaces of the first pair of gate structures face second end surfaces of the second pair of gate structure. The first and second end surfaces of the first and second pair of gate structures are in physical contact with first and second sidewalls of the isolation structure, respectively. The semiconductor device further includes an isolation structure interposed between the first and second pairs of gate structures. An aspect ratio of the isolation structure is smaller than a combined aspect ratio of the first pair of gate structures.

公开(公告)号：US11521969B2

公开(公告)日：2022-12-06

申请号：US16937297

申请日：2020-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Shuo Chen ,  Chia-Der Chang ,  Yi-Jing Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/311 ,  H01L21/3213

Abstract: A semiconductor device with an isolation structure and a method of fabricating the same are disclosed. The semiconductor device includes first and second fin structures disposed on a substrate and first and second pairs of gate structures disposed on the first and second fin structures. The first end surfaces of the first pair of gate structures face second end surfaces of the second pair of gate structure. The first and second end surfaces of the first and second pair of gate structures are in physical contact with first and second sidewalls of the isolation structure, respectively. The semiconductor device further includes an isolation structure interposed between the first and second pairs of gate structures. An aspect ratio of the isolation structure is smaller than a combined aspect ratio of the first pair of gate structures.

公开(公告)号：US20220085167A1

公开(公告)日：2022-03-17

申请号：US17456799

申请日：2021-11-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sherry Li ,  Chia-Der Chang ,  Yi-Jing Lee

IPC: H01L29/10 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/165

Abstract: The present disclosure describes a method for forming ultra-thin fins with a tapered bottom profile for improved structural rigidity and gate control characteristics. The method includes forming a fin structure that includes an epitaxial layer portion and a doped region portion surrounded by an isolation region so that a top section of the epitaxial layer portion is above the isolation region. The method also includes depositing a silicon-based layer on the top portion of the epitaxial layer above the isolation region and annealing the silicon-based layer to reflow the silicon-based layer. The method further includes etching the silicon-based layer and the fin structure above the isolation region to form a first bottom tapered profile in the fin structure above the isolation region and annealing the fin structure to form a second bottom tapered profile below the first bottom tapered profile and above the isolation region.

公开(公告)号：US11276693B2

公开(公告)日：2022-03-15

申请号：US16047141

申请日：2018-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Jing Lee ,  Li-Wei Chou ,  Ming-Hua Yu

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/36 ,  H01L29/161 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/306 ,  H01L21/02

Abstract: A semiconductor device and method of forming the same are disclosed. The method of forming a semiconductor device includes providing a substrate, an isolation structure over the substrate, and at least two fins extending from the substrate and through the isolation structure; etching the at least two fins, thereby forming at least two trenches; growing first epitaxial features in the at least two trenches; growing second epitaxial features over the first epitaxial features in a first growth condition; and after the second epitaxial features reach a target critical dimension, growing the second epitaxial features in a second growth condition different from the first growth condition.

公开(公告)号：US11056578B2

公开(公告)日：2021-07-06

申请号：US16725655

申请日：2019-12-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Jing Lee ,  Ming-Hua Yu

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/04 ,  H01L27/092

Abstract: In a method for manufacturing a semiconductor device, an isolation insulating layer is formed over a fin structure. A first portion of the fin structure is exposed from and a second portion of the fin structure is embedded in the isolation insulating layer. A dielectric layer is formed over sidewalls of the first portion of the fin structure. The first portion of the fin structure and a part of the second portion of the fin structure in a source/drain region are removed, thereby forming a trench. A source/drain epitaxial structure is formed in the trench using one of a first process or a second process. The first process comprises an enhanced epitaxial growth process having an enhanced growth rate for a preferred crystallographic facet, and the second process comprises using a modified etch process to reduce a width of the source/drain epitaxial structure.

公开(公告)号：US10727229B2

公开(公告)日：2020-07-28

申请号：US15816386

申请日：2017-11-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Jing Lee ,  Tsz-Mei Kwok ,  Ming-Hua Yu

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/06 ,  H01L29/08 ,  H01L27/092 ,  H01L21/306 ,  H01L21/311 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate; an isolation structure over the substrate; and two fins in a first region of the semiconductor device extending from the substrate and through the isolation structure. Each of the two fins has a channel region and two source/drain (S/D) regions sandwiching the channel region. The semiconductor device further includes a gate stack over the isolation structure and engaging the channel regions of the two fins; and four S/D features over the S/D regions of the two fins. Each of the four S/D features includes a lower portion and an upper portion over the lower portion. Each of the lower portions of the four S/D features has a cross-sectional profile that is wider at its bottom than at its top. The upper portions of the four S/D features merge into two merged S/D features with one on each side of the gate stack.

公开(公告)号：US10714487B2

公开(公告)日：2020-07-14

申请号：US16234283

申请日：2018-12-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Jing Lee ,  Tsz-Mei Kwok ,  Ming-Hua Yu ,  Kun-Mu Li

IPC: H01L27/11 ,  H01L27/02 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165

Abstract: A semiconductor device includes a transistor, an isolation structure, and a fin sidewall structure. The transistor includes a fin extending from a substrate and an epitaxy structure grown on the fin. The isolation structure is above the substrate. The fin sidewall structure is above the isolation structure and is on a sidewall of the epitaxy structure. A method for manufacturing the semiconductor device is also disclosed.

公开(公告)号：US09768178B2

公开(公告)日：2017-09-19

申请号：US14938311

申请日：2015-11-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Jing Lee ,  Tsz-Mei Kwok ,  Ming-Hua Yu ,  Kun-Mu Li

IPC: H01L27/11 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L27/1104 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/7853

Abstract: A semiconductor device includes a substrate, a first semiconductor fin, a second semiconductor fin, an n-type epitaxy structure, a p-type epitaxy structure, and a plurality of dielectric fin sidewall structures. The first semiconductor fin is disposed on the substrate. The second semiconductor fin is disposed on the substrate and adjacent to the first semiconductor fin. The n-type epitaxy structure is disposed on the first semiconductor fin. The p-type epitaxy structure is disposed on the second semiconductor fin and separated from the n-type epitaxy structure. The dielectric fin sidewall structures are disposed on opposite sides of at least one of the n-type epitaxy structure and the p-type epitaxy structure.

公开(公告)号：US20240355910A1

公开(公告)日：2024-10-24

申请号：US18760829

申请日：2024-07-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Jing Lee ,  Ming-Hua Yu

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/08 ,  H01L29/167 ,  H01L29/36 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7851 ,  H01L21/28088 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/4966

Abstract: A method includes recessing a semiconductor fin to form a recess, wherein the semiconductor fin protrudes higher than isolation regions on opposite sides of the semiconductor fin, and performing a first epitaxy to grow a first epitaxy layer extending into the recess. The first epitaxy is performed using a first process gas comprising a silicon-containing gas, silane, and a phosphorous-containing gas. The first epitaxy layer has a first phosphorous atomic percentage. The method further includes performing a second epitaxy to grow a second epitaxy layer extending into the recess and over the first epitaxy layer. The second epitaxy is performed using a second process gas comprising the silicon-containing gas, silane, and the phosphorous-containing gas. The second epitaxy layer has a second phosphorous atomic percentage higher than the first phosphorous atomic percentage.

公开(公告)号：US12075607B2

公开(公告)日：2024-08-27

申请号：US18069765

申请日：2022-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Jing Lee ,  Tsz-Mei Kwok ,  Ming-Hua Yu ,  Kun-Mu Li

IPC: H10B10/00 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165

CPC classification number: H10B10/12 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/7848 ,  H01L29/7853 ,  H01L29/165

Abstract: A device includes a semiconductor substrate, a semiconductor fin, a gate structure, a first source/drain epitaxy structure, a second source/drain epitaxy structure, a first dielectric fin sidewall structure, a second dielectric fin sidewall structure. The semiconductor fin is over the semiconductor substrate. The semiconductor fin includes a channel portion and recessed portions on opposite sides of the channel portion. The gate structure is over the channel portion of the semiconductor fin. The first source/drain epitaxy structure and the second source/drain epitaxy structure are over the recessed portions of the semiconductor fin, respectively. The first source/drain epitaxy structure has a round surface. The first dielectric fin sidewall structure and the second dielectric fin sidewall structure are on opposite sides of the first source/drain epitaxy structure. The round surface of the first source/drain epitaxy structure is directly above the first dielectric fin sidewall structure.