公开(公告)号：US20230197801A1

公开(公告)日：2023-06-22

申请号：US18168422

申请日：2023-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Pei-Yu Wang ,  Chi On Chui

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/775 ,  H01L29/08 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786 ,  H01L21/306 ,  H01L21/3065

CPC classification number: H01L29/41733 ,  H01L29/6653 ,  H01L29/66742 ,  H01L29/66553 ,  H01L29/0673 ,  H01L29/7834 ,  H01L29/775 ,  H01L29/66439 ,  H01L29/0847 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/66545 ,  H01L21/30604 ,  H01L21/3065

Abstract: In an embodiment, a device includes: a first nanostructure over a substrate, the first nanostructure including a channel region and a first lightly doped source/drain region, the first lightly doped source/drain region adjacent the channel region; a first epitaxial source/drain region wrapped around four sides of the first lightly doped source/drain region; an interlayer dielectric over the first epitaxial source/drain region; a source/drain contact extending through the interlayer dielectric, the source/drain contact wrapped around four sides of the first epitaxial source/drain region; and a gate stack adjacent the source/drain contact and the first epitaxial source/drain region, the gate stack wrapped around four sides of the channel region.

公开(公告)号：US11616143B2

公开(公告)日：2023-03-28

申请号：US17005134

申请日：2020-08-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Yuan Chen ,  Huan-Chieh Su ,  Pei-Yu Wang ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

Abstract: Embodiments of the present disclosure provide a method for forming backside metal contacts with reduced Cgd and increased speed. Particularly, source/drain features on the drain side, or source/drain features without backside metal contact, are recessed from the backside to the level of the inner spacer to reduce Cgd. Some embodiments of the present disclosure use a sacrificial liner to protect backside alignment feature during backside processing, thus, preventing shape erosion of metal conducts and improving device performance.

公开(公告)号：US20210366716A1

公开(公告)日：2021-11-25

申请号：US17391834

申请日：2021-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Wang ,  Zhi-Chang Lin ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L21/28 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/3213 ,  H01L21/3105 ,  H01L29/66 ,  H01L27/088

Abstract: A semiconductor device includes a substrate, a first semiconductor fin and a second semiconductor fin protruding from the substrate, an isolation feature disposed on the substrate and on sidewalls of the first and second semiconductor fins, a gate structure disposed on the isolation feature. The semiconductor device also includes a dielectric fin disposed on the isolation feature and sandwiched between the first and second semiconductor fins. A middle portion of the dielectric fin separates the gate structure into a first gate structure segment engaging the first semiconductor fin and a second gate structure segment engaging the second semiconductor fin.

公开(公告)号：US20210343639A1

公开(公告)日：2021-11-04

申请号：US17158409

申请日：2021-01-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Wang ,  Yu-Xuan Huang

IPC: H01L23/522 ,  H01L27/088 ,  H01L21/768

Abstract: An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, an epitaxial regrowth layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is over a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is over a backside of the source epitaxial structure and a backside of the drain epitaxial structure. The epitaxial regrowth layer is on the backside of a first one of the source epitaxial structure and the drain epitaxial structure. The backside via extends through the backside dielectric layer and overlaps the epitaxial regrowth layer.

公开(公告)号：US20210217890A1

公开(公告)日：2021-07-15

申请号：US17216241

申请日：2021-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chieh Yang ,  Li-Yang Chuang ,  Pei-Yu Wang ,  Wei Ju Lee ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/08

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.

公开(公告)号：US10964816B2

公开(公告)日：2021-03-30

申请号：US16441080

申请日：2019-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chieh Yang ,  Li-Yang Chuang ,  Pei-Yu Wang ,  Wei Ju Lee ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/08

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.

公开(公告)号：US20210091179A1

公开(公告)日：2021-03-25

申请号：US16582694

申请日：2019-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Wang ,  Wei Ju Lee

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L29/45 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306

Abstract: A semiconductor device includes a substrate, semiconductor wires disposed over the substrate, a gate structure wrapping around each of the semiconductor wires, and an epitaxial source/drain (S/D) feature in contact with the semiconductor wires. A portion of the epitaxial S/D feature is horizontally surrounded by an air gap.

公开(公告)号：US10756197B2

公开(公告)日：2020-08-25

申请号：US16585741

申请日：2019-09-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsiung Lin ,  Chia-Hao Chang ,  Chih-Hao Wang ,  Wai-Yi Lien ,  Chih-Chao Chou ,  Pei-Yu Wang

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/764 ,  H01L21/28 ,  H01L27/092 ,  H01L21/8238

Abstract: In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.

公开(公告)号：US10756196B2

公开(公告)日：2020-08-25

申请号：US16584826

申请日：2019-09-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsiung Lin ,  Chia-Hao Chang ,  Chih-Hao Wang ,  Wai-Yi Lien ,  Chih-Chao Chou ,  Pei-Yu Wang

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/764 ,  H01L21/28 ,  H01L27/092 ,  H01L21/8238

Abstract: In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.

公开(公告)号：US10510860B2

公开(公告)日：2019-12-17

申请号：US15801171

申请日：2017-11-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsiung Lin ,  Chia-Hao Chang ,  Chih-Hao Wang ,  Wai-Yi Lien ,  Chih-Chao Chou ,  Pei-Yu Wang

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/764 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092

Abstract: In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.