公开(公告)号：US20220223785A1

公开(公告)日：2022-07-14

申请号：US17369484

申请日：2021-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Min Lee ,  Shy-Jay Lin ,  Yen-Lin Huang ,  MingYuan Song ,  Tung Ying Lee

IPC: H01L43/04 ,  H01L43/10 ,  H01L27/22 ,  H01L43/14

Abstract: Semiconductor device includes pair of active devices, composite spin Hall electrode, and a magnetic tunnel junction. Composite spin Hall electrode is electrically connected to pair of active devices. Magnetic tunnel junction is disposed on opposite side of composite spin hall electrode with respect to pair of active devices. Spin Hall electrode includes pair of heavy metal layers, and spacer layer disposed in between pair of heavy metal layers. Pair of heavy metal layers is made of a heavy metal in a metastable state. Spacer layer comprises first material different from the pair of heavy metal layers.

公开(公告)号：US11387360B2

公开(公告)日：2022-07-12

申请号：US16874526

申请日：2020-05-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng Yuan ,  Ming-Shiang Lin ,  Chia-Cheng Ho ,  Jin Cai ,  Tzu-Chung Wang ,  Tung Ying Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L21/8234

Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.

公开(公告)号：US20210305390A1

公开(公告)日：2021-09-30

申请号：US17346378

申请日：2021-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung Ying Lee ,  Kai-Tai Chang ,  Meng-Hsuan Hsiao

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238

Abstract: The current disclosure describes techniques for forming gate-all-around (“GAA”) devices from stacks of separately formed nanowire semiconductor strips. The separately formed nanowire semiconductor strips are tailored for the respective GAA devices. A trench is formed in a first stack of epitaxy layers to define a space for forming a second stack of epitaxy layers. The trench bottom is modified to have determined or known parameters in the shapes or crystalline facet orientations. The known parameters of the trench bottom are used to select suitable processes to fill the trench bottom with a relatively flat base surface.

公开(公告)号：US11038036B2

公开(公告)日：2021-06-15

申请号：US16536113

申请日：2019-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung Ying Lee ,  Kai-Tai Chang ,  Meng-Hsuan Hsiao

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238

Abstract: The current disclosure describes techniques for forming gate-all-around (“GAA”) devices from stacks of separately formed nanowire semiconductor strips. The separately formed nanowire semiconductor strips are tailored for the respective GAA devices. A trench is formed in a first stack of epitaxy layers to define a space for forming a second stack of epitaxy layers. The trench bottom is modified to have determined or known parameters in the shapes or crystalline facet orientations. The known parameters of the trench bottom are used to select suitable processes to fill the trench bottom with a relatively flat base surface.

公开(公告)号：US11038034B2

公开(公告)日：2021-06-15

申请号：US16394152

申请日：2019-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung Ying Lee ,  Shao-Ming Yu ,  Tzu-Chung Wang

IPC: H01L21/28 ,  H01L29/423 ,  H01L27/22 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66

Abstract: In some embodiments, a method for forming an integrated chip (IC) is provided. The method incudes forming an interlayer dielectric (ILD) layer over a substrate. A first opening is formed in the ILD layer and in a first region of the IC. A second opening is formed in the ILD layer and in a second region of the IC. A first high-k dielectric layer is formed lining both the first and second openings. A second dielectric layer is formed on the first high-k dielectric layer and lining the first high-k dielectric layer in both the first and second regions. The second high-k dielectric layer is removed from the first region. A conductive layer is formed over both the first and second high-k dielectric layers, where the conductive layer contacts the first high-k dielectric layer in the first region and contacts the second high-k dielectric in the second region.

公开(公告)号：US11007005B2

公开(公告)日：2021-05-18

申请号：US15988624

申请日：2018-05-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung Ying Lee ,  Ziwei Fang ,  Yee-Chia Yeo ,  Meng-Hsuan Hsiao

IPC: A61B18/14 ,  A61B17/295 ,  A61B17/29 ,  A61B17/285 ,  A61B17/28 ,  A61B90/00 ,  H01L29/417 ,  H01L29/78 ,  A61B18/00

Abstract: In a method of forming a FinFET, a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is recessed so that a remaining layer of the first sacrificial layer is formed on the isolation insulating layer and an upper portion of the source/drain structure is exposed. A second sacrificial layer is formed on the remaining layer and the exposed source/drain structure. The second sacrificial layer and the remaining layer are patterned, thereby forming an opening. A dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first and second sacrificial layers are removed to form a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.

公开(公告)号：US10930498B2

公开(公告)日：2021-02-23

申请号：US16598275

申请日：2019-10-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Chung Wang ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Tung Ying Lee

IPC: H01L21/336 ,  H01L21/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/775 ,  H01L21/8238 ,  H01L21/8234

Abstract: The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.

公开(公告)号：US20200343302A1

公开(公告)日：2020-10-29

申请号：US16394152

申请日：2019-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung Ying Lee ,  Shao-Ming Yu ,  Tzu-Chung Wang

IPC: H01L27/24 ,  H01L27/22 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28

Abstract: In some embodiments, a method for forming an integrated chip (IC) is provided. The method incudes forming an interlayer dielectric (ILD) layer over a substrate. A first opening is formed in the ILD layer and in a first region of the IC. A second opening is formed in the ILD layer and in a second region of the IC. A first high-k dielectric layer is formed lining both the first and second openings. A second dielectric layer is formed on the first high-k dielectric layer and lining the first high-k dielectric layer in both the first and second regions. The second high-k dielectric layer is removed from the first region. A conductive layer is formed over both the first and second high-k dielectric layers, where the conductive layer contacts the first high-k dielectric layer in the first region and contacts the second high-k dielectric in the second region.

公开(公告)号：US20200279998A1

公开(公告)日：2020-09-03

申请号：US16289733

申请日：2019-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Chao Lin ,  Jui-Ming Chen ,  Shao-Ming Yu ,  Tung Ying Lee ,  Yu-Sheng Chen

IPC: H01L45/00 ,  H01L27/24

Abstract: In some embodiments, the present disclosure relates to an integrated chip including a phase change material disposed over a bottom electrode and configured to change from a crystalline structure to an amorphous structure upon temperature changes. A top electrode is disposed over an upper surface of the phase change material. A via electrically contacts a top surface of the top electrode. Further, a maximum width of the upper surface of the phase change material is less than a maximum width of a bottom surface of the phase change material.

公开(公告)号：US10714592B2

公开(公告)日：2020-07-14

申请号：US15798270

申请日：2017-10-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching Cheng ,  Chen-Feng Hsu ,  Tzu-Chiang Chen ,  Tung Ying Lee ,  Wei-Sheng Yun ,  Yu-Lin Yang

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  B82Y10/00

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.