公开(公告)号：US10804367B2

公开(公告)日：2020-10-13

申请号：US15719686

申请日：2017-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Wei-Sheng Yun ,  I-Sheng Chen ,  Shao-Ming Yu ,  Tzu-Chiang Chen ,  Chih Chieh Yeh

IPC: H01L29/165 ,  H01L21/8236 ,  H01L27/092 ,  H01L29/51 ,  H01L29/66 ,  H01L29/10 ,  H01L27/06 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/775 ,  H01L29/40

Abstract: A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer.

公开(公告)号：US20190393357A1

公开(公告)日：2019-12-26

申请号：US16235987

申请日：2018-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Sheng Chen ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Carlos H. Diaz

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

Abstract: A nanowire FET device includes a vertical stack of nanowire strips configured as the semiconductor body. One or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. Inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. Source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips.

公开(公告)号：US10403550B2

公开(公告)日：2019-09-03

申请号：US15885359

申请日：2018-01-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Li Chiang ,  Chao-Ching Cheng ,  Chih-Liang Chen ,  Tzu-Chiang Chen ,  Ta-Pen Guo ,  Yu-Lin Yang ,  I-Sheng Chen ,  Szu-Wei Huang

IPC: H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.

公开(公告)号：US10355102B2

公开(公告)日：2019-07-16

申请号：US15941798

申请日：2018-03-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching Cheng ,  Yu-Lin Yang ,  Wei-Sheng Yun ,  Chen-Feng Hsu ,  Tzu-Chiang Chen

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306

Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.

公开(公告)号：US10170374B2

公开(公告)日：2019-01-01

申请号：US15632449

申请日：2017-06-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Sheng Chen ,  Tzu-Chiang Chen ,  Cheng-Hsien Wu ,  Chih-Chieh Yeh ,  Chih-Sheng Chang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02

Abstract: A semiconductor device includes at least one n-channel, at least one p-channel, at least one first high-k dielectric sheath, at least one second high-k dielectric sheath, a first metal gate electrode and a second metal gate electrode. The first high-k dielectric sheath surrounds the n-channel. The second high-k dielectric sheath surrounds the p-channel. The first high-k dielectric sheath and the second high-k dielectric sheath comprise different high-k dielectric materials. The first metal gate electrode surrounds the first high-k dielectric sheath. The second metal gate electrode surrounds the second high-k dielectric sheath.

公开(公告)号：US12170323B2

公开(公告)日：2024-12-17

申请号：US18365995

申请日：2023-08-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Yi-Tse Hung ,  Hung-Li Chiang ,  Tzu-Chiang Chen ,  Lain-Jong Li ,  Jin Cai

IPC: H01L29/00 ,  H01L29/06 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes forming a first sacrificial layer over a substrate, and forming a sandwich structure over the first sacrificial layer. The sandwich structure includes a first isolation layer, a two-dimensional material over the first isolation layer, and a second isolation layer over the two-dimensional material. The method further includes forming a second sacrificial layer over the sandwich structure, forming a first source/drain region and a second source/drain region on opposing ends of, and contacting sidewalls of, the two-dimensional material, removing the first sacrificial layer and the second sacrificial layer to generate spaces, and forming a gate stack filling the spaces.

公开(公告)号：US20240379440A1

公开(公告)日：2024-11-14

申请号：US18782274

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Tzu-Ang Chao ,  Chun-Chieh Lu ,  Hung-Li Chiang ,  Tzu-Chiang Chen ,  Lain-Jong Li

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10K10/46 ,  H10K71/12 ,  H10K85/20

Abstract: A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin.

公开(公告)号：US12046665B2

公开(公告)日：2024-07-23

申请号：US18160256

申请日：2023-01-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Hung-Li Chiang ,  Chun-Chieh Lu ,  Ming-Yang Li ,  Tzu-Chiang Chen

IPC: H01L29/76 ,  H01L29/04 ,  H01L29/20 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7606 ,  H01L29/04 ,  H01L29/2003 ,  H01L29/454 ,  H01L29/66795 ,  H01L29/785

Abstract: A process is provided to fabricate a finFET device having a semiconductor layer of a two-dimensional “2D” semiconductor material. The semiconductor layer of the 2D semiconductor material is a thin film layer formed over a dielectric fin-shaped structure. The 2D semiconductor layer extends over at least three surfaces of the dielectric fin structure, e.g., the upper surface and two sidewall surfaces. A vertical protrusion metal structure, referred to as “metal fin structure”, is formed about an edge of the dielectric fin structure and is used as a seed to grow the 2D semiconductor material.

公开(公告)号：US11929425B2

公开(公告)日：2024-03-12

申请号：US17352507

申请日：2021-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Chung Wang ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Tung Ying Lee

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/785 ,  H01L2029/7858

Abstract: The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.

公开(公告)号：US11594615B2

公开(公告)日：2023-02-28

申请号：US17216448

申请日：2021-03-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching Cheng ,  Yu-Lin Yang ,  Wei-Sheng Yun ,  Chen-Feng Hsu ,  Tzu-Chiang Chen

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/306 ,  H01L29/04 ,  H01L29/08 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/775

Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.