公开(公告)号：US20210305382A1

公开(公告)日：2021-09-30

申请号：US16948745

申请日：2020-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu HUANG ,  Li-Zhen YU ,  Chia-Hao CHANG ,  Cheng-Chi CHUANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/417 ,  H01L29/423

Abstract: A semiconductor device includes a metal gate structure having sidewall spacers disposed on sidewalls of the metal gate structure. In some embodiments, a top surface of the metal gate structure is recessed with respect to a top surface of the sidewall spacers. The semiconductor device may further include a metal cap layer disposed over and in contact with the metal gate structure, where a first width of a bottom portion of the metal cap layer is greater than a second width of a top portion of the metal cap layer. In some embodiments, the semiconductor device may further include a dielectric material disposed on either side of the metal cap layer, where the sidewall spacers and a portion of the metal gate structure are disposed beneath the dielectric material.

公开(公告)号：US20210234036A1

公开(公告)日：2021-07-29

申请号：US17233451

申请日：2021-04-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Kuan-Ting PAN ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/16 ,  H01L21/8234

Abstract: A semiconductor device structure includes a fin structure, a semiconductive capping layer, an oxide layer, and a gate structure. The fin structure protrudes above a substrate. The semiconductive capping layer wraps around three sides of a channel region of the fin structure. The oxide layer wraps around three sides of the semiconductive capping layer. A thickness of a top portion of the semiconductive capping layer is less than a thickness of a top portion of the oxide layer. The gate structure wraps around three sides of the oxide layer.

公开(公告)号：US20200381531A1

公开(公告)日：2020-12-03

申请号：US16599972

申请日：2019-10-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting CHUNG ,  Ching-Wei TSAI ,  Kuan-Lun CHENG

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/161 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8234

Abstract: Multi-gate semiconductor devices and methods for forming thereof including forming air gaps between the gate and the adjacent source/drain features. A first fin element including a plurality of silicon layers is disposed on a substrate, a first gate structure is formed over a channel region of the first fin element. An air gap is formed such that it is disposed on a sidewall of the portion of the first gate structure. An epitaxial source/drain feature abuts the air gap. A portion of the first gate structure may also be disposed between first and second layers of the plurality of silicon layers.

公开(公告)号：US20200176449A1

公开(公告)日：2020-06-04

申请号：US16781485

申请日：2020-02-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHING ,  Shi Ning JU ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L27/092 ,  H01L21/28 ,  H01L21/308 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L29/51

Abstract: Aspects of the disclosure provide a semiconductor device and a method for forming the semiconductor device. The semiconductor device includes a plurality of nanostructures stacked over a substrate in a vertical direction, a source/drain terminal adjoining the plurality of nanostructures, and a gate structure around the plurality of nanostructures. The gate structure includes a metal cap connecting adjacent two of the plurality of nanostructures and a metal layer partially surrounding the plurality of nanostructures.

公开(公告)号：US20200083107A1

公开(公告)日：2020-03-12

申请号：US16681621

申请日：2019-11-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Shi-Ning JU ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L21/8234 ,  H01L27/088

Abstract: Methods for manufacturing semiconductor structures are provided. The method includes alternately stacking first epitaxy layers and second epitaxy layers to form a semiconductor stack and forming a first mask structure and a second mask structure over the semiconductor stack. The method further includes forming spacers on sidewalls of the second mask and patterning the semiconductor stack to form a first fin structure covered by the first mask structure and a second fin structure covered by the second mask structure and the spacers. The method further includes removing the first epitaxy layers of the first fin structure to form first nanostructures and removing the first epitaxy layers of the second fin structure to form second nanostructures. In addition, the second nanostructures are wider than the first nanostructures.

公开(公告)号：US20200020689A1

公开(公告)日：2020-01-16

申请号：US16034520

申请日：2018-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tetsu OHTOU ,  Ching-Wei TSAI ,  Jiun-Jia HUANG ,  Kuan-Lun CHENG ,  Chi-Hsing HSU

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: The present disclosure describes a method for the formation of gate-all-around nano-sheet FETs with tunable performance. The method includes disposing a first and a second vertical structure with different widths over a substrate, where the first and the second vertical structures have a top portion comprising a multilayer nano-sheet stack with alternating first and second nano-sheet layers. The method also includes disposing a sacrificial gate structure over the top portion of the first and second vertical structures; depositing an isolation layer over the first and second vertical structures so that the isolation layer surrounds a sidewall of the sacrificial gate structure; etching the sacrificial gate structure to expose each multilayer nano-sheet stack from the first and second vertical structures; removing the second nano-sheet layers from each exposed multilayer nano-sheet stack to form suspended first nano-sheet layers; forming a metal gate structure to surround the suspended first nano-sheet layers.

公开(公告)号：US20190237464A1

公开(公告)日：2019-08-01

申请号：US16380818

申请日：2019-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHING ,  Kuan-Lun CHENG ,  Chih-Hao WANG ,  Sai-Hooi YEONG ,  Tzer-Min SHEN ,  Chi-Hsing HSU

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/26506 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/40111 ,  H01L29/511 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Devices and methods of forming a FET including a substrate having a first fin and a second fin extending therefrom. A high-k gate dielectric layer and a ferroelectric insulator layer are deposited over the first fin and the second fin. In some embodiments, a dummy gate layer is deposited over the ferroelectric insulator layer over the first fin and the second fin to form a first gate stack over the first fin and a second gate stack over the second fin. The dummy gate layer of the first gate stack is then removed (while maintaining the ferroelectric insulator layer) to form a first trench. And the dummy gate layer and the ferroelectric insulator layer of the second gate stack are removed to form a second trench. At least one metal gate layer is formed in the first trench and the second trench.

公开(公告)号：US20190172926A1

公开(公告)日：2019-06-06

申请号：US16204849

申请日：2018-11-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHING ,  Chih-Hao WANG ,  Ching-Wei TSAI ,  Kuan-Lun CHENG

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/45 ,  H01L21/3065 ,  H01L21/02

Abstract: A method of forming a fin field effect transistors (finFET) on a substrate includes forming a fin structure on the substrate, forming a protective layer on the fin structure, and forming a polysilicon structure on the protective layer. The method further includes modifying the polysilicon structure such that a first horizontal dimension of a first portion of the modified polysilicon structure is smaller than a second horizontal dimension of a second portion of the modified polysilicon structure. The method further includes replacing the modified polysilicon structure with a gate structure having a first horizontal dimension of a first portion of the gate structure that is smaller than a second horizontal dimension of a second portion of the gate structure.

公开(公告)号：US20250133808A1

公开(公告)日：2025-04-24

申请号：US18988547

申请日：2024-12-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Kai-Chieh YANG ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L21/28 ,  H10D30/01 ,  H10D30/62 ,  H10D64/01 ,  H10D64/66

Abstract: Aspects of the disclosure provide a method for forming a fin field effect transistor (FinFET) incorporating a fin top hardmask on top of a channel region of a fin. Because of the presence of the fin top hardmask, a gate height of the FinFET can be reduced without affecting proper operations of vertical gate channels on sidewalls of the fin. Consequently, parasitic capacitance between a gate stack and source/drain contacts of the FinFET can be reduced by lowering the gate height of the FinFET.

公开(公告)号：US20250113602A1

公开(公告)日：2025-04-03

申请号：US18979048

申请日：2024-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Ruei JHAN ,  Chih-Hao WANG ,  Kuo-Cheng CHIANG ,  Kuan-Lun CHENG ,  Kuan-Ting PAN

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A device includes a substrate, a first semiconductor channel over the substrate, and a second semiconductor channel over the substrate laterally offset from the first semiconductor channel. A first gate structure and a second gate structure are over and laterally surround the first and second semiconductor channels, respectively. A first inactive fin is between the first gate structure and the second gate structure. A dielectric feature over the inactive fin includes multiple layers of dielectric material formed through alternating deposition and etching steps.