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95 条记录 (耗时 0.03 秒)

    Vehicle surroundings monitoring apparatus
    67.
    发明申请
    Vehicle surroundings monitoring apparatus 有权
    车辆周边监控装置

    公开(公告)号：US20100066518A1

    公开(公告)日：2010-03-18

    申请号：US12584869

    申请日：2009-09-14

    申请人： Kenichi Ohshima ,  Shigenobu Saigusa ,  Yasuhiro Konishi

    发明人： Kenichi Ohshima ,  Shigenobu Saigusa ,  Yasuhiro Konishi

    IPC分类号： B60Q1/00

    CPC分类号： B60R1/12 ,  B60R1/00 ,  B60R2001/1253 ,  B60R2300/102 ,  B60R2300/105

    摘要： A vehicle surroundings monitoring apparatus includes: a plurality of imaging units which capture an external region of a present-vehicle and output images; a display unit which is installed in an interior of the present-vehicle; a selector which selects an image to be displayed on the display unit from the images output from the imaging units; and a display control unit which displays the images output from the imaging units on the display unit so as to be switched in accordance with a selection by the selector and displays an image indicator display indicating a display region in the external region of the present-vehicle corresponding to the images so as to be switched by the selector on the display unit.

    摘要翻译： 车辆周边监视装置包括：多个成像单元，其捕获本车辆的外部区域并输出图像; 安装在本车内部的显示单元; 选择器，其从从所述成像单元输出的图像中选择要在所述显示单元上显示的图像; 以及显示控制单元，其将根据所述选择器的选择切换的所述成像单元输出的图像显示在所述显示单元上，并且在所述当前车辆的外部区域中显示指示显示区域的图像指示符显示器 对应于图像，以便由显示单元上的选择器切换。

    Synchronous semiconductor memory device with NOEMI output buffer circuit
    68.
    发明授权
    Synchronous semiconductor memory device with NOEMI output buffer circuit 失效
    具有NOEMI输出缓冲电路的同步半导体存储器件

    公开(公告)号：US06597630B1

    公开(公告)日：2003-07-22

    申请号：US10253883

    申请日：2002-09-25

    申请人： Takashi Kubo ,  Yasuhiro Konishi ,  Takashi Kono

    发明人： Takashi Kubo ,  Yasuhiro Konishi ,  Takashi Kono

    IPC分类号： G11C700

    CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1072

    摘要： There are provided a control signal generation circuit receiving an external instruction input in synchronization with a clock signal to generate a control signal for defining a data output period in response to the external instruction, and an output buffer circuit receiving data read from a memory array for output to an output node for the data output period, and there is further provided an output control circuit for controlling turning first, second and third transistors on and off, the output control circuit in the data out period turning on and off one of the first and second transistors complementarily in response to the read data and also turning on the third transistor in response to the control signal.

    摘要翻译： 提供了一个与时钟信号同步地接收外部指令输入的控制信号发生电路，以产生用于响应于外部指令定义数据输出周期的控制信号，以及一个从存储器阵列读取的数据的输出缓冲电路， 输出到用于数据输出周期的输出节点，并且还提供一个输出控制电路，用于控制第一，第二和第三晶体管的导通和截止，输出控制电路在数据输出周期内接通和关断第一， 和第二晶体管互补地响应于读取的数据，并且还响应于控制信号接通第三晶体管。

    Clock synchronous semiconductor memory device allowing testing by low speed tester
    69.
    发明授权
    Clock synchronous semiconductor memory device allowing testing by low speed tester 失效
    时钟同步半导体存储器件允许通过低速测试仪测试

    公开(公告)号：US06489819B1

    公开(公告)日：2002-12-03

    申请号：US09179411

    申请日：1998-10-27

    申请人： Takashi Kono ,  Takeshi Hamamoto ,  Yasuhiro Konishi

    发明人： Takashi Kono ,  Takeshi Hamamoto ,  Yasuhiro Konishi

    IPC分类号： G11C700

    CPC分类号： G11C29/14

    摘要： Pulses are generated using an edge of a clock signal applied from a low speed tester as a trigger, and internal clock signals are generated utilizing the pulses. Internal circuitry is operated in synchronization with the internal clock signals. Thus a synchronous semiconductor device operating at high speed can be tested using a low speed tester.

    摘要翻译： 使用从低速测试仪施加的时钟信号的边沿作为触发产生脉冲，并且使用脉冲产生内部时钟信号。 内部电路与内部时钟信号同步工作。 因此，可以使用低速测试仪来测试以高速操作的同步半导体器件。

    Synchronous semiconductor memory having read data mask controlled output circuit
    70.
    发明授权
    Synchronous semiconductor memory having read data mask controlled output circuit 失效
    具有读取数据掩模控制输出电路的同步半导体存储器

    公开(公告)号：US6157992A

    公开(公告)日：2000-12-05

    申请号：US768089

    申请日：1996-12-16

    申请人： Seiji Sawada ,  Yasuhiro Konishi

    发明人： Seiji Sawada ,  Yasuhiro Konishi

    IPC分类号： G11C11/407 ,  G11C7/00 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409 ,  G06F12/00

    CPC分类号： G11C7/1072

    摘要： A read enable signal OEMF activated in response to an input command is applied to an N minus 2 clock shift circuit included in an output control circuit for implementation of ZCAS latency. An output signal of the N minus 2 clock shift circuit and an internal mask instructing signal activated in response to an external mask instructing signal are logically processed and applied to a one-clock shift circuit. According to an output signal OEMQM of one-clock shift circuit, a data output enable signal OEM controlling activation/inactivation of an output buffer circuit is activated/inactivated. Data output controlling portion occupying area of a synchronous dynamic random access memory is reduced and timings of activation/inactivation of data output by different commands are made the same.

    摘要翻译： 响应于输入命令而激活的读使能信号OEMF被施加到包括在用于实现ZCAS延迟的输出控制电路中的N-2时钟移位电路。 N减2时钟移位电路的输出信号和响应于外部掩码指示信号而被激活的内部掩码指示信号被逻辑地处理并施加到一个时钟的移位电路。 根据一时钟移位电路的输出信号OEMQM，激活/禁止输出缓冲电路的数据输出使能信号OEM控制激活/失活。 同步动态随机存取存储器的数据输出控制部占用面积减少，不同命令输出的数据的激活/失活定时相同。