公开(公告)号：US07983109B2

公开(公告)日：2011-07-19

申请号：US12890636

申请日：2010-09-25

申请人： Satoru Hanzawa ,  Hitoshi Kume

发明人： Satoru Hanzawa ,  Hitoshi Kume

IPC分类号： G11C8/00 ,  G11C5/02 ,  G11C5/06 ,  G11C7/00

CPC分类号： G11C13/0023 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2013/0083 ,  G11C2213/71 ,  G11C2213/72

摘要： A phase change memory capable of highly reliable operations is provided. A semiconductor device has a memory array having a structure in which memory cells are stacked including memory layers using a chalcogenide material and diodes, and initialization conditions and write conditions are changed according to the layer in which a selected memory cell is positioned. The initialization conditions and write conditions (herein, reset conditions) are changed according to the operation by selecting a current mirror circuit according to the operation and by a control mechanism of a reset current in a voltage select circuit and the current mirror circuit.

摘要翻译： 提供了具有高度可靠的操作的相变存储器。 半导体器件具有存储器阵列，其具有使用硫族化物材料和二极管层叠存储层的存储单元的结构，并且根据所选择的存储单元所在的层来改变初始化条件和写入条件。 初始化条件和写入条件（这里是复位条件）根据操作通过根据操作选择电流镜电路和通过电压选择电路和电流镜电路中的复位电流的控制机构而改变。

公开(公告)号：US07978524B2

公开(公告)日：2011-07-12

申请号：US12862350

申请日：2010-08-24

申请人： Satoru Hanzawa ,  Takeshi Sakata

发明人： Satoru Hanzawa ,  Takeshi Sakata

IPC分类号： G11C16/06

CPC分类号： G11C29/787 ,  G11C7/14 ,  G11C11/1673 ,  G11C11/1693

摘要： A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.

摘要翻译： 虚拟单元包括多个用于存储“1”或“0”的第一存储单元MC，其布置在多个字线WR0至WR7与多个第一数据线D0至D7之间的交点处，多个第一 用于存储“1”或“0”的虚拟单元MCH，布置在字线WR0至WR7和第一虚拟数据线之间的交点处，以及多个第二虚拟单元MCL，用于存储“0” 字线WR0〜WR7与第二伪数据线DD1的交点。

公开(公告)号：US07864568B2

公开(公告)日：2011-01-04

申请号：US12516690

申请日：2006-12-07

申请人： Yoshihisa Fujisaki ,  Satoru Hanzawa ,  Kenzo Kurotsuchi ,  Nozomu Matsuzaki ,  Norikatsu Takaura

发明人： Yoshihisa Fujisaki ,  Satoru Hanzawa ,  Kenzo Kurotsuchi ,  Nozomu Matsuzaki ,  Norikatsu Takaura

IPC分类号： G11C11/00

CPC分类号： H01L45/144 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2213/75 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233

摘要： In a semiconductor storage device such as a phase change memory, a technique which can realize high integration is provided. The semiconductor storage device includes a phase change thin film 101 having two stable phases of a crystal state with low electric resistance and an amorphous state with high electric resistance, upper plug electrodes 102 and 103 provided on one side of the phase change thin film 101, a lower electrode 104 provided on the other side of the phase change thin film 101, a selecting transistor 114 whose drain/source terminals are connected to the upper plug electrode 102 and the lower electrode 104, and a selecting transistor 115 whose drain/source terminals are connected to the upper plug electrode 103 and the lower electrode 104, and a first memory cell is configured with the selecting transistor 114 and a phase change region 111 in the phase change thin film 101 sandwiched between the upper plug electrode 102 and the lower electrode 104, and a second memory cell is configured with the selecting transistor 115 and a phase change region 112 in the phase change thin film 101 sandwiched between the upper plug electrode 103 and the lower electrode 104.

摘要翻译： 在诸如相变存储器的半导体存储装置中，提供了可以实现高集成度的技术。 半导体存储装置包括：具有低电阻的晶体状态的两个稳定相和具有高电阻的非晶态的相变薄膜101，设置在相变薄膜101一侧的上部插塞电极102和103， 设置在相变薄膜101的另一侧的下部电极104，漏极/源极端子连接到上部插塞电极102和下部电极104的选择晶体管114，以及选择晶体管115，其漏极/源极端子 连接到上插头电极103和下电极104，并且第一存储单元配置有夹在上插头电极102和下电极之间的相变薄膜101中的选择晶体管114和相变区域111 104，并且第二存储单元配置有夹在b中的相变薄膜101中的选择晶体管115和相变区域112 在上塞电极103和下电极104之间。

公开(公告)号：US07830706B2

公开(公告)日：2010-11-09

申请号：US12335418

申请日：2008-12-15

申请人： Satoru Hanzawa ,  Hitoshi Kume

发明人： Satoru Hanzawa ,  Hitoshi Kume

IPC分类号： G11C11/00

CPC分类号： G11C13/0023 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2013/0083 ,  G11C2213/71 ,  G11C2213/72

摘要： A phase change memory capable of highly reliable operations is provided. A semiconductor device has a memory array having a structure in which memory cells are stacked including memory layers using a chalcogenide material and diodes, and initialization conditions and write conditions are changed according to the layer in which a selected memory cell is positioned. The initialization conditions and write conditions (herein, reset conditions) are changed according to the operation by selecting a current mirror circuit according to the operation and by a control mechanism of a reset current in a voltage select circuit and the current mirror circuit.

摘要翻译： 提供了具有高度可靠的操作的相变存储器。 半导体器件具有存储器阵列，其具有使用硫族化物材料和二极管层叠存储层的存储单元的结构，并且根据所选择的存储单元所在的层来改变初始化条件和写入条件。 初始化条件和写入条件（这里是复位条件）根据操作通过根据操作选择电流镜电路和通过电压选择电路和电流镜电路中的复位电流的控制机构而改变。

公开(公告)号：US07804717B2

公开(公告)日：2010-09-28

申请号：US12474887

申请日：2009-05-29

申请人： Satoru Hanzawa ,  Takeshi Sakata

发明人： Satoru Hanzawa ,  Takeshi Sakata

IPC分类号： G11C16/06

CPC分类号： G11C29/787 ,  G11C7/14 ,  G11C11/1673 ,  G11C11/1693

摘要： A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.

摘要翻译： 虚拟单元包括多个用于存储“1”或“0”的第一存储单元MC，其布置在多个字线WR0至WR7与多个第一数据线D0至D7之间的交点处，多个第一 用于存储“1”或“0”的虚拟单元MCH，布置在字线WR0至WR7和第一虚拟数据线之间的交点处，以及多个第二虚拟单元MCL，用于存储“0” 字线WR0〜WR7与第二伪数据线DD1的交点。

公开(公告)号：US20100182828A1

公开(公告)日：2010-07-22

申请号：US12688886

申请日：2010-01-17

申请人： Akio SHIMA ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Toshiyuki Mine ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Kenzo Kurotsuchi ,  Satoru Hanzawa

发明人： Akio SHIMA ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Toshiyuki Mine ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Kenzo Kurotsuchi ,  Satoru Hanzawa

IPC分类号： G11C11/00 ,  H01L47/00 ,  G11C8/00

CPC分类号： H01L27/2481 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/79 ,  H01L27/2454 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1683

摘要： There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.

摘要翻译： 提供了能够进一步减小存储单元的尺寸并增加存储容量的半导体存储装置。 每个包括形成在半导体衬底上的晶体管的多个存储单元以及具有由电压供应改变并连接在晶体管的源极和漏极端子之间的电阻值的可变电阻器件被纵向排列成阵列以构成三维存储器 单元格阵列。 存储单元结构具有双通道结构，其中开关晶体管的内部填充有可变电阻元件，特别是相变材料。 通过施加电压来切换开关晶体管，以增加沟道电阻，使得电流在内部相变材料中流动以操作存储器。

公开(公告)号：US07170792B2

公开(公告)日：2007-01-30

申请号：US11126214

申请日：2005-05-11

申请人： Satoru Hanzawa ,  Takeshi Sakata

发明人： Satoru Hanzawa ,  Takeshi Sakata

IPC分类号： G11C11/34

CPC分类号： G11C8/08 ,  G11C11/4074 ,  G11C11/4085

摘要： A semiconductor device to output voltages at three levels to a word driver while alleviating the breakdown voltage in the MOS transistor. This invention is comprised of a breakdown-voltage reducing MOS transistor inserted in the word driver and two NMOS transistors to supply a read-out voltage to a word line. The word driver is moreover controlled by different voltage amplitudes on the main word lines and the common word lines.

摘要翻译： 一种半导体器件，用于将三电平的电压输出到字驱动器，同时减轻MOS晶体管中的击穿电压。 本发明包括插入字驱动器中的击穿电压降低MOS晶体管和两个NMOS晶体管，以将读出电压提供给字线。 此外，字驱动器通过主字线和公用字线上的不同电压幅度进行控制。

公开(公告)号：US20060148135A1

公开(公告)日：2006-07-06

申请号：US11368603

申请日：2006-03-07

申请人： Hideyuki Matsuoka ,  Kiyoo Itoh ,  Motoyasu Terao ,  Satoru Hanzawa ,  Takeshi Sakata

发明人： Hideyuki Matsuoka ,  Kiyoo Itoh ,  Motoyasu Terao ,  Satoru Hanzawa ,  Takeshi Sakata

IPC分类号： H01L21/50

CPC分类号： H01L27/2454 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is achieved by the present invention. Besides low power consumption during read operation, the invention also provides phase change memory having low power consumption even during write operation. Phase change memory also has stable read-out operation.

公开(公告)号：US06903966B2

公开(公告)日：2005-06-07

申请号：US10863748

申请日：2004-06-09

申请人： Takeshi Sakata ,  Satoru Hanzawa ,  Hideyuki Matsuoka ,  Katsuro Watanabe ,  Kenchi Ito

发明人： Takeshi Sakata ,  Satoru Hanzawa ,  Hideyuki Matsuoka ,  Katsuro Watanabe ,  Kenchi Ito

IPC分类号： G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08 ,  G11C11/00

CPC分类号： H01L27/226 ,  B82Y10/00 ,  G11C11/16

摘要： Disclosed are a fast, highly-integrated and highly-reliable magnetoresistive random access memory (MRAM) and a semiconductor device which uses the MRAM. The semiconductor device performs the read-out operation of the MRAM using memory cells for storing information by using a change in magnetoresistance of a magnetic tunnel junction (MTJ) element with a high S/N ratio. Each memory cell includes an MTJ element and a bipolar transistor. The read-out operation is carried out by selecting a word line, amplifying a current flowing in the MTJ element of a target memory cell by the bipolar transistor and outputting the amplified current to an associated read data line.

摘要翻译： 公开了一种快速，高度集成和高可靠性的磁阻随机存取存储器（MRAM）和使用MRAM的半导体器件。 半导体器件使用存储单元执行MRAM的读出操作，用于通过使用具有高S / N比的磁性隧道结（MTJ）元件的磁阻的变化来存储信息。 每个存储单元包括MTJ元件和双极晶体管。 通过选择字线，通过双极晶体管放大在目标存储单元的MTJ元件中流动的电流并将放大的电流输出到相关联的读取数据线来执行读出操作。

公开(公告)号：US06611474B2

公开(公告)日：2003-08-26

申请号：US10201317

申请日：2002-07-24

申请人： Satoru Hanzawa ,  Takeshi Sakata

发明人： Satoru Hanzawa ,  Takeshi Sakata

IPC分类号： G11C11407

CPC分类号： G11C8/08 ,  G11C11/4074 ,  G11C11/4085

摘要： A semiconductor device to output voltages at three levels to a word driver while alleviating the breakdown voltage in the MOS transistor. This invention is comprised of a breakdown-voltage reducing MOS transistor inserted in the word driver and two NMOS transistors to supply a read-out voltage to a word line. The word driver is moreover controlled by different voltage amplitudes on the main word lines and the common word lines.