公开(公告)号：US07530049B2

公开(公告)日：2009-05-05

申请号：US11440086

申请日：2006-05-25

申请人： Sachiko Kobayashi ,  Toshiya Kotani

发明人： Sachiko Kobayashi ,  Toshiya Kotani

IPC分类号： G06F17/50

CPC分类号： G03F1/68 ,  G03F1/36

摘要： A mask manufacturing system and a mask data creating method reusing data for processing information and environment in the past to reduce a photomask developing period, and a manufacturing method of a semiconductor device are disclosed. According to one aspect of the present invention, it is provided a mask manufacturing system comprising a storage device storing processing data for semiconductor integrated circuits processed in the past, a plurality of operation processing modules, a module selecting section selecting at least one operation processing modules, an optical proximity effect correction section executing optical proximity effect correction to a processing object data and generating a correction data by utilizing past correction information applied for a stored data equivalent to the processing object data, a converting section converting the processing object data into mask data, and a drawing system drawing a mask pattern based on the mask data.

摘要翻译： 掩模制造系统和掩模数据创建方法重复利用用于处理信息和环境的数据以减少光掩模生长期，以及半导体器件的制造方法。 根据本发明的一个方面，提供了一种掩模制造系统，包括存储用于过去处理的半导体集成电路的处理数据的存储装置，多个操作处理模块，模块选择部分，其选择至少一个操作处理模块 光学接近效应校正部分，对处理对象数据执行光学邻近效应校正，并通过利用应用于与处理对象数据相当的存储数据的过去校正信息产生校正数据;转换部分，将处理对象数据转换成掩模数据 以及基于掩模数据绘制掩模图案的绘图系统。

公开(公告)号：US07523437B2

公开(公告)日：2009-04-21

申请号：US11012492

申请日：2004-12-16

申请人： Suigen Kyoh ,  Toshiya Kotani ,  Soichi Inoue

发明人： Suigen Kyoh ,  Toshiya Kotani ,  Soichi Inoue

IPC分类号： G06F16/50

CPC分类号： G03F1/36 ,  G03F7/70441

摘要： Disclosed is a method of producing a pattern for a semiconductor device, comprising extracting part of a pattern layout, perturbing a pattern included in the part of the pattern layout to generate a perturbation pattern, correcting the perturbation pattern, predicting a first pattern, to be formed on a wafer, from the corrected perturbation pattern, acquiring a first difference between the perturbation pattern and the first pattern, and storing information concerning the perturbation pattern including information concerning the first difference.

摘要翻译： 公开了一种制造用于半导体器件的图案的方法，包括提取图案布局的一部分，扰乱包含在图案布局部分中的图案以产生扰动图案，校正扰动图案，预测第一图案，为 形成在晶片上，从校正的扰动图案获取扰动图案和第一图案之间的第一个差异，以及存储关于包含关于第一个差异的信息的扰动图案的信息。

公开(公告)号：US07337426B2

公开(公告)日：2008-02-26

申请号：US11115187

申请日：2005-04-27

申请人： Toshiya Kotani ,  Shigeki Nojima ,  Kazuhito Kobayashi

发明人： Toshiya Kotani ,  Shigeki Nojima ,  Kazuhito Kobayashi

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： There is disclosed a pattern correcting method comprising extracting a correction pattern, at least the one or more correction patterns being included in a first design pattern formed on a substrate, acquiring layout information from the first design pattern, the layout information affecting a finished plane shape of the correction pattern on the substrate, determining contents of correction onto the correction pattern on the basis of the layout information, generating a design pattern-2 corresponding to the layout information so as to be associated with the correction pattern, and correcting the correction pattern in accordance with the contents of correction corresponding to the design pattern-2.

摘要翻译： 公开了一种图案校正方法，包括提取校正图案，至少一个或多个校正图案包括在形成在基板上的第一设计图案中，从第一设计图案获取布局信息，影响成品平面形状的布局信息 基于所述布局信息确定校正图案的校正内容，生成与所述布局信息对应的设计图案-2以与所述校正图案相关联，以及校正所述校正图案 按照与设计模式相对应的修正内容2。

公开(公告)号：US07266801B2

公开(公告)日：2007-09-04

申请号：US11012613

申请日：2004-12-16

申请人： Toshiya Kotani ,  Suigen Kyoh ,  Hirotaka Ichikawa

发明人： Toshiya Kotani ,  Suigen Kyoh ,  Hirotaka Ichikawa

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： There is disclosed a method of correcting a design pattern considering a process margin between layers of a semiconductor integrated circuit, including calculating a first pattern shape corresponding to a processed pattern shape of a first layer based on a first design pattern, calculating a second pattern shape corresponding to a processed pattern shape of a second layer based on a second design pattern, calculating a third pattern shape using a Boolean operation between the first and second pattern shapes, determining whether or not an evaluation value obtained from the third pattern shape satisfies a predetermined value, and correcting at least one of the first and second design patterns if it is determined that the evaluation value does not satisfy the predetermined value.

摘要翻译： 公开了一种考虑半导体集成电路的层之间的处理余量来校正设计图案的方法，包括基于第一设计图案计算与第一层的处理图案形状相对应的第一图案形状，计算第二图案形状 对应于基于第二设计图案的第二层的处理图案形状，使用第一和第二图案形状之间的布尔运算来计算第三图案形状，确定从第三图案形状获得的评估值是否满足预定的 值，并且如果确定所述评估值不满足所述预定值，则校正所述第一和第二设计图案中的至少一个。

公开(公告)号：US07181707B2

公开(公告)日：2007-02-20

申请号：US10385628

申请日：2003-03-12

申请人： Toshiya Kotani ,  Satoshi Tanaka ,  Koji Hashimoto ,  Soichi Inoue ,  Ichiro Mori

发明人： Toshiya Kotani ,  Satoshi Tanaka ,  Koji Hashimoto ,  Soichi Inoue ,  Ichiro Mori

IPC分类号： G06F17/50 ,  G06K9/00

CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a method of setting a process parameter for use in manufacturing a semiconductor integrated circuit, comprising correcting a first pattern by using process parameter information to obtain a second pattern, the first pattern being one which corresponds to a design layout of the semiconductor integrated circuit, predicting a third pattern by using the process parameter information, the third pattern being one which corresponds to the second pattern and which is to be formed on a semiconductor wafer in an etching process, obtaining an evaluation value by comparing the third pattern with the first pattern, determining whether the evaluation value satisfies a preset condition, and changing the process parameter information when the evaluation value is found not to satisfy the preset condition.

摘要翻译： 公开了一种设置用于制造半导体集成电路的工艺参数的方法，包括通过使用工艺参数信息来校正第一图案以获得第二图案，第一图案是对应于半导体集成电路的设计布局的图案 ，通过使用处理参数信息来预测第三图案，在蚀刻工艺中，第三图案是对应于第二图案并且将形成在半导体晶片上的图案，通过将第三图案与第一图案进行比较来获得评估值 判定评估值是否满足预设条件，以及当评估值不满足预设条件时，改变处理参数信息。

公开(公告)号：US20070028205A1

公开(公告)日：2007-02-01

申请号：US11492802

申请日：2006-07-26

申请人： Ayako Nakano ,  Toshiya Kotani ,  Atsushi Watanabe

发明人： Ayako Nakano ,  Toshiya Kotani ,  Atsushi Watanabe

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A design data processing method in a semiconductor device includes extracting, from design data, a graphic in which there exist a first wiring and a second wiring which is orthogonal to the first wiring, and changing a portion where the first wiring is orthogonal to the second wiring to make connection at an angle other than 90 degrees, thereby preparing new design data.

摘要翻译： 半导体装置中的设计数据处理方法包括从设计数据提取存在与第一布线正交的第一布线和第二布线的图形，以及将第一布线正交于第二布线的部分 接线以90度以外的角度进行连接，从而准备新的设计数据。

公开(公告)号：US20060197136A1

公开(公告)日：2006-09-07

申请号：US11346293

申请日：2006-02-03

申请人： Takuya Futatsuyama ,  Toshiya Kotani ,  Hiromitsu Mashita ,  Atsushi Maesono ,  Ayako Nakano ,  Tadahito Fujisawa

发明人： Takuya Futatsuyama ,  Toshiya Kotani ,  Hiromitsu Mashita ,  Atsushi Maesono ,  Ayako Nakano ,  Tadahito Fujisawa

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  H01L27/11517

摘要： According to this invention, the NAND type flash memory of high reliability is realized. It provides a semiconductor memory device comprising: a plurality of memory cells; a plurality of word lines formed by a first gate wiring layer; a plurality of first transistors for providing voltages to said word lines; and electrical connections for connection said word lines and sources or drains of said first transistors, said electrical connections being formed of both first wirings of a first wiring layer formed above said first gate wiring layer and second wirings of a second wiring layers formed above said first wiring layer.

摘要翻译： 根据本发明，实现了高可靠性的NAND型闪速存储器。 它提供一种半导体存储器件，包括：多个存储单元; 由第一栅极布线层形成的多个字线; 用于向所述字线提供电压的多个第一晶体管; 以及用于连接所述字线和所述第一晶体管的源极或漏极的电连接，所述电连接由形成在所述第一栅极布线层上方的第一布线层的第一布线和形成在所述第一晶体管上方的第二布线层的第二布线形成 接线层。

公开(公告)号：US07065739B2

公开(公告)日：2006-06-20

申请号：US10331005

申请日：2002-12-27

申请人： Sachiko Kobayashi ,  Toshiya Kotani ,  Satoshi Tanaka ,  Susumu Watanabe ,  Mitsuhiro Yano

发明人： Sachiko Kobayashi ,  Toshiya Kotani ,  Satoshi Tanaka ,  Susumu Watanabe ,  Mitsuhiro Yano

IPC分类号： G06F17/50 ,  G03F1/00

CPC分类号： G03F1/36 ,  G03F7/70441

摘要： A pattern correction method executed by a computer includes a first correction and a second correction. The first correction is executed by calculating a correction value, in consideration for an optical proximity effect, for edges (first edges) meeting a condition among the edges constituting a designed pattern. Subsequently, The second correction is executed for an edge (second edge) which does not meet the condition, by use of the correction value of any one of the edges (first edges) adjacent to the second edge among the first edges for which the first correction is executed, thus connecting the corrected first edge and the corrected second edge by a line segment. The pattern is corrected to a shape suitable for a mask drawing and a check with simple processing.

摘要翻译： 由计算机执行的图案校正方法包括第一校正和第二校正。 对于构成设计图案的边缘中满足条件的边缘（第一边缘），考虑光学邻近效应来计算校正值来执行第一校正。 随后，对于不符合条件的边缘（第二边缘），通过使用与第一边缘相邻的边缘（第一边缘）中的任何一个边缘（第一边缘）的第一边缘的第一边缘 执行校正，从而将校正的第一边缘和校正的第二边缘连接到线段。 该图案被校正为适于掩模绘图和具有简单处理的检查的形状。

公开(公告)号：US20060093926A1

公开(公告)日：2006-05-04

申请号：US11259069

申请日：2005-10-27

申请人： Tadahito Fujisawa ,  Takeshi Ito ,  Toshiya Kotani

发明人： Tadahito Fujisawa ,  Takeshi Ito ,  Toshiya Kotani

IPC分类号： G03C5/00 ,  G03F1/00

CPC分类号： G03F7/70441 ,  G03F1/36

摘要： A mask pattern data generating method is disclosed, which comprises preparing mask pattern data which corresponds to a design pattern including a pair of line patterns formed of two line patterns, and disposing an auxiliary pattern which is un-transferable to a resist film at a center of a space region between the pair of line patterns, in which the disposing of the auxiliary pattern includes obtaining a shape of the auxiliary pattern which meets formulae in which a width in the short edge direction of the auxiliary pattern, a space width between the auxiliary pattern and one of the pair of line patterns, a wavelength of an exposure light emitted by a projection aligner using a photo mask at exposure, and a numerical apertures of a projection lens of the projection aligner are defined as parameters, and disposing the obtained auxiliary pattern at the center of the space region.

公开(公告)号：US20050251781A1

公开(公告)日：2005-11-10

申请号：US11115322

申请日：2005-04-27

申请人： Toshiya Kotani ,  Shigeki Nojima ,  Shimon Maeda

发明人： Toshiya Kotani ,  Shigeki Nojima ,  Shimon Maeda

IPC分类号： G03C5/00 ,  G03F1/36 ,  G03F1/68 ,  G03F9/00 ,  G06F17/50 ,  H01L21/027

CPC分类号： G03F1/36

摘要： A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not the length of the measured edge is shorter than a predetermined value, extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value, and reshaping the design pattern to match positions of the two extracted vertexes with each other.

摘要翻译： 公开了一种相对于设计图案的微小步骤校正设计图案的设计图案校正方法，其包括提取从设计图案的顶点延伸的两个边缘中的至少一个，测量提取的边缘的长度， 确定测量的边缘的长度是否短于预定值，如果确定提取的边缘的长度短于预定值，则提取连接到所提取的边缘的两个顶点，并且重新设计匹配的设计模式 两个提取的顶点的位置彼此相对。