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    Semiconductor structure and method for forming the same
    62.
    发明授权
    Semiconductor structure and method for forming the same 有权

    公开(公告)号：US10937946B2

    公开(公告)日：2021-03-02

    申请号：US16541172

    申请日：2019-08-15

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hui-Lin Wang ,  Chia-Chang Hsu ,  Rai-Min Huang

    IPC: H01L43/02 ,  H01L43/08 ,  H01L27/22 ,  H01L43/12 ,  H01L43/10

    Abstract: A semiconductor structure is provided in the present invention, including a substrate having a device region and an alignment mark region defined thereon, a dielectric layer disposed on the substrate, a conductive via formed in the dielectric layer on the device region, a first trench formed in the dielectric layer on the alignment mark, a plurality of second trenches formed in the dielectric layer directly under the first trench and exposed from a bottom surface of the first trench, and a memory stacked structure disposed on the dielectric layer, directly covering a top surface of the conductive via and filling into the first trench and the second trench.

    MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
    64.
    发明申请
    MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20200295257A1

    公开(公告)日：2020-09-17

    申请号：US16885233

    申请日：2020-05-27

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chen-Yi Weng ,  Jing-Yin Jhang ,  Hui-Lin Wang ,  Chin-Yang Hsieh

    IPC: H01L43/12 ,  H01L43/10 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

    Abstract: A manufacturing method of a semiconductor device includes the following steps. A first inter-metal dielectric (IMD) layer is formed on a substrate. A cap layer is formed on the first IMD layer. A connection structure is formed on the substrate and penetrates the cap layer and the first IMD layer. A magnetic tunnel junction (MTJ) stack is formed on the connection structure and the cap layer. A patterning process is performed to the MTJ stack for forming a MTJ structure on the connection structure and removing the cap layer. A second IMD layer is formed on the first IMD layer and surrounds the MTJ structure. The semiconductor device includes the substrate, the connection structure, the first IMD layer, the MTJ structure, and the second IMD layer. The dielectric constant of the first IMD layer is lower than the dielectric constant of the second IMD layer.

    MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    65.
    发明申请
    MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20200185597A1

    公开(公告)日：2020-06-11

    申请号：US16216969

    申请日：2018-12-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kun-Ju Li ,  Hsin-Jung Liu ,  I-Ming Tseng ,  Chau-Chung Hou ,  Yu-Lung Shih ,  Fu-Chun Hsiao ,  Hui-Lin Wang ,  Tzu-Hsiang Hung ,  Chih-Yueh Li ,  Ang Chan ,  Jing-Yin Jhang

    IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  H01L43/12

    Abstract: A memory device includes an insulation layer, a memory cell region and an alignment mark region are defined on the insulation layer, an interconnection structure disposed in the insulation layer, a dielectric layer disposed on the insulation layer and the interconnection structure, the dielectric layer is disposed within the memory cell region and the alignment mark region, a conductive via plug disposed on the interconnection structure within the memory cell region, the conductive via plug has a concave top surface, an alignment mark trench penetrating the dielectric layer within the alignment mark region, a bottom electrode disposed on the conductive via plug within the memory cell region and disposed in the alignment mark trench within the alignment mark region, and a magnetic tunnel junction (MTJ) structure disposed on the bottom electrode within the memory cell region and disposed in the alignment mark trench within the alignment mark region.

    SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF
    69.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF 审中-公开

    公开(公告)号：US20240315142A1

    公开(公告)日：2024-09-19

    申请号：US18134039

    申请日：2023-04-13

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hui-Lin Wang

    IPC: H10N50/10 ,  H10B61/00 ,  H10N50/01

    CPC classification number: H10N50/10 ,  H10B61/00 ,  H10N50/01

    Abstract: A semiconductor memory device includes a substrate, a first interlayer dielectric layer, a second interlayer dielectric layer, a via in the second interlayer dielectric layer in a memory region, and a data storage structure on the via. The second interlayer dielectric layer includes a first recess structure and a second recess structure. The first recess structure has a first recessed thickness between the bottom surface of the data storage structure and the lowest point of the second interlayer dielectric layer in the memory area. The second recess structure has a second recessed thickness between the bottom surface of the data storage structure and the lowest point of the logic circuit region. The first recessed thickness ranges between 300-650 angstroms, and the second recessed thickness ranges between 300-800 angstroms.

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