公开(公告)号：US06358821B1

公开(公告)日：2002-03-19

申请号：US09619376

申请日：2000-07-19

申请人： Subhash Gupta ,  Simon Chooi ,  Sudipto Ranendra Roy ,  Paul Kwok Keung Ho ,  Xu Yi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Leonard Sudijono

发明人： Subhash Gupta ,  Simon Chooi ,  Sudipto Ranendra Roy ,  Paul Kwok Keung Ho ,  Xu Yi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Leonard Sudijono

IPC分类号： H01L2122

CPC分类号： H01L21/3221 ,  C23C14/165 ,  H01L21/2885

摘要： A method of preventing copper transport on a semiconductor wafer, comprising the following steps. A semiconductor wafer having a front side and a backside is provided. Metal, selected from the group comprising aluminum, aluminum-copper, aluminum-silicon, and aluminum-copper-silicon is sputtered on the backside of the wafer to form a layer of metal. The back side sputtered aluminum layer may be partially oxidized at low temperature to further decrease the copper penetration possibility and to also provide greater flexibility in subsequent copper interconnect related processing. Once the back side layer is in place, the wafer can be processed as usual. The sputtered back side aluminum layer can be removed during final backside grinding.

摘要翻译： 一种防止半导体晶片上的铜传输的方法，包括以下步骤。 提供具有正面和背面的半导体晶片。 从包括铝，铝 - 铜，铝 - 硅和铝 - 铜 - 硅的组中选择的金属溅射在晶片的背面以形成一层金属。 背面溅射的铝层可以在低温下部分氧化，以进一步降低铜的渗透可能性，并且在随后的铜互连相关处理中也提供更大的灵活性。 一旦背面层就位，就可以照常处理晶片。 最后的背面研磨可以除去溅射的背面铝层。

公开(公告)号：US06348407B1

公开(公告)日：2002-02-19

申请号：US09805955

申请日：2001-03-15

申请人： Subhash Gupta ,  Yi Xu ,  Simon Chooi ,  Mei Sheng Zhou

发明人： Subhash Gupta ,  Yi Xu ,  Simon Chooi ,  Mei Sheng Zhou

IPC分类号： H01L214763

CPC分类号： H01L21/76826 ,  H01L21/31058 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76829

摘要： This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the use an alternate etch stop in dual damascene interconnects that improves adhesion between low dielectric constant organic materials. In addition, the etch stop material is a silicon containing material and is transformed into a low dielectric constant material (k=3.5 to 5), which becomes silicon-rich silicon oxide after UV radiation and silylation, oxygen plasma.

摘要翻译： 本发明涉及用于半导体集成电路器件的制造方法，更具体地说，涉及在双镶嵌互连中使用改进低介电常数有机材料之间的粘附性的交替蚀刻停止。 此外，蚀刻停止材料是含硅材料，并被转变成低介电常数材料（k = 3.5至5），其在UV辐射和甲硅烷基化之后变成富氧氧化硅，氧等离子体。

公开(公告)号：US06274499B1

公开(公告)日：2001-08-14

申请号：US09442493

申请日：1999-11-19

申请人： Subhash Gupta ,  Paul Kwok Keung Ho ,  Mei Sheng Zhou ,  Ramasamy Chockalingam

发明人： Subhash Gupta ,  Paul Kwok Keung Ho ,  Mei Sheng Zhou ,  Ramasamy Chockalingam

IPC分类号： H01L21302

CPC分类号： H01L21/76801 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76807 ,  H01L21/76834

摘要： In accordance with the objects of this invention a new method to prevent copper contamination of the intermetal dielectric layer during etching, CMP, or post-etching and post-CMP cleaning by forming a dielectric cap for isolation of the underlying dielectric layer is described. In one embodiment of the invention, a dielectric layer is provided overlying a semiconductor substrate. A dielectric cap layer is deposited overlying the dielectric layer. A via is patterned and filled with a metal layer and planarized. A copper layer is deposited overlying the planarized metal layer and dielectric cap layer. The copper layer is etched to form a copper line wherein the dielectric cap layer prevents copper contamination of the dielectric layer during etching and cleaning. In another embodiment of the invention, a dielectric layer is provided overlying a semiconductor substrate. A dielectric cap layer is deposited overlying the dielectric layer. A dual damascene opening is formed through the dielectric cap layer and the dielectric layer. A copper layer is deposited overlying a barrier metal layer over the dielectric cap layer and filling the dual damascene opening. The copper layer is polished back to leave the copper layer only within the dual damascene opening where the dielectric cap layer prevents copper contamination of the dielectric layer during polishing and cleaning.

摘要翻译： 根据本发明的目的，描述了通过形成用于隔离下面介电层的电介质盖，在蚀刻，CMP或后蚀刻和后CMP清洗中防止金属间电介质层的铜污染的新方法。 在本发明的一个实施例中，提供覆盖在半导体衬底上的电介质层。 介电覆盖层沉积在介电层上。 通孔被图案化并填充有金属层并且被平坦化。 沉积在平坦化的金属层和电介质盖层上的铜层。 铜层被蚀刻以形成铜线，其中电介质盖层在蚀刻和清洁期间防止电介质层的铜污染。 在本发明的另一个实施例中，提供覆盖半导体衬底的电介质层。 介电覆盖层沉积在介电层上。 通过电介质盖层和电介质层形成双镶嵌开口。 将铜层沉积在电介质盖层上方的阻挡金属层上，并填充双镶嵌开口。 将铜层抛光回来，仅在双镶嵌开口中留下铜层，其中介电盖层在抛光和清洁期间防止电介质层的铜污染。

公开(公告)号：US06251786B1

公开(公告)日：2001-06-26

申请号：US09390783

申请日：1999-09-07

申请人： Mei Sheng Zhou ,  Paul Kwok Keung Ho ,  Subhash Gupta

发明人： Mei Sheng Zhou ,  Paul Kwok Keung Ho ,  Subhash Gupta

IPC分类号： H01L2100

CPC分类号： H01L21/76834 ,  H01L21/3212 ,  H01L21/76807 ,  H01L21/7684 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dual damascene structure is created in a dielectric layer, the structure contains a barrier layer while a cap layer may or may not be provided over the layer of dielectric for further protection of the dual damascene structure. The surface of the copper in the dual damascene structure is recessed, a thin film is deposited and planarized/partially removed by either CMP or a plasma etch thereby providing a sturdy surface above the copper of the dual damascene structure that prevents dishing and erosion of this surface.

摘要翻译： 在电介质层中产生双镶嵌结构，该结构包含阻挡层，而覆盖层可以设置在电介质层上，也可以不设置在电介质层上，以进一步保护双镶嵌结构。 双镶嵌结构中的铜的表面是凹进的，通过CMP或等离子体蚀刻沉积并平面化/部分去除薄膜，从而在双镶嵌结构的铜上方提供坚固的表面，防止该镶嵌结构的凹陷和侵蚀 表面。

公开(公告)号：US06184138B2

公开(公告)日：2001-02-06

申请号：US09390782

申请日：1999-09-07

申请人： Paul Kwok Keung Ho ,  Mei Sheng Zhou ,  Subhash Gupta

发明人： Paul Kwok Keung Ho ,  Mei Sheng Zhou ,  Subhash Gupta

IPC分类号： H01L2144

CPC分类号： H01L21/76843 ,  H01L21/7684 ,  H01L21/76874 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879

摘要： A new method is provided to construct a copper dual damascene structure. A layer of IMD is deposited over the surface of a substrate. A cap layer is deposited over this layer of IMD, the dual damascene structure is then patterned through the cap layer and into the layer of IMD. A barrier layer is blanket deposited, a copper seed layer is deposited over the barrier layer. The dual damascene structure is then filled with a spin-on material. The barrier layer and the copper seed layer are removed above the cap layer; the cap layer can be partially removed or can be left in place. The spin on material remains in place in the via and trench opening during the operation of removing the copper seed layer and the barrier layer from above the cap surface thereby protecting the inside surfaces of these openings. The spin-on material is next removed from the dual damascene structure and copper is deposited. The cap layer that is still present above the surface of the IMD protects the dielectric from being contaminated with copper solution during the deposition of the copper. The excess copper is removed using a touch-up CMP. The cap layer over the surface of the IMD can, after the copper has been deposited, be removed if this is so desired. As a final step in the process, a liner or oxidation/diffusion protection layer is deposited over the dual damascene structure and its surrounding area.

摘要翻译： 提供了一种构建铜双镶嵌结构的新方法。 一层IMD沉积在衬底的表面上。 覆盖层沉积在IMD的该层上，然后将双镶嵌结构通过盖层图案化并进入IMD层。 阻挡层被覆盖沉积，铜晶种层沉积在阻挡层上。 然后用镶嵌材料填充双镶嵌结构。 在盖层上除去阻挡层和铜籽晶层; 盖层可以被部分地去除或可以留在原处。 在从盖表面上方去除铜种子层和阻挡层的操作期间，材料上的旋转保持在通孔和沟槽开口中的适当位置，从而保护这些开口的内表面。 随后从双镶嵌结构中去除旋涂材料，并沉积铜。 仍然存在于IMD表面之上的盖层保护铜在沉积期间不被铜溶液污染。 使用上层CMP去除多余的铜。 如果这样做是希望的话，在沉积铜之后，IMD表面上的盖层可以被去除。 作为该方法的最后一步，衬垫或氧化/扩散保护层沉积在双镶嵌结构及其周围区域上。

公开(公告)号：US5866448A

公开(公告)日：1999-02-02

申请号：US902757

申请日：1997-07-30

申请人： Yelehanka Ramachandramurthy Pradeep ,  Tang Kok Hiang ,  Mei Sheng Zhou

发明人： Yelehanka Ramachandramurthy Pradeep ,  Tang Kok Hiang ,  Mei Sheng Zhou

IPC分类号： H01L21/336 ,  H01L21/8238

CPC分类号： H01L29/6659 ,  H01L21/823814 ,  Y10S438/963

摘要： A method for fabrication of a lightly-doped-drain (LDD) structure for self aligned polysilicon gate MOSFETs is described wherein a polymer layer, formed along the sidewall during the patterning process of the polysilicon gate electrode, is used to mask the source/drain ion implant. The sidewall polymer layer replaces the conventional silicon oxide sidewall as an LDD spacer and offers improved thickness control as well as an improved sequence of processing steps whereby the deposition of a spacer oxide layer onto the gate oxide is eliminated. A cap oxide layer first deposited over the gate polysilicon layer. This oxide layer is then patterned and etched using RIE under conditions which form a polymer sidewall layer along the edges of the cap oxide pattern. The polysilicon layer is then etched, and has a pattern concentric with the cap oxide pattern but wider by the thickness of the polymer sidewall. After removal of the polymer and residual photoresist, the source/drain implant is performed, followed by removal of the polysilicon lip by RIE using the cap oxide as a mask. The LDD implant is then performed.

摘要翻译： 描述了一种制造用于自对准多晶硅栅极MOSFET的轻掺杂漏极（LDD）结构的方法，其中在多晶硅栅电极的图案化工艺期间沿侧壁形成的聚合物层用于掩蔽源/漏 离子植入。 侧壁聚合物层代替常规的氧化硅侧壁作为LDD间隔物，并提供改进的厚度控制以及改进的处理步骤顺序，从而消除间隔氧化物层沉积到栅极氧化物上。 首先沉积在栅极多晶硅层上的覆盖氧化物层。 然后使用RIE在沿着氧化物图案的边缘形成聚合物侧壁层的条件下对该氧化物层进行构图和蚀刻。 然后蚀刻多晶硅层，并且具有与盖氧化物图案同心的图案，但是通过聚合物侧壁的厚度更宽。 在去除聚合物和残余光致抗蚀剂之后，进行源极/漏极注入，随后通过RIE使用帽氧化物作为掩模去除多晶硅唇缘。 然后执行LDD植入。

公开(公告)号：US5801083A

公开(公告)日：1998-09-01

申请号：US954046

申请日：1997-10-20

申请人： Bo Yu ,  Qing Hua Zhong ,  Jian Hui Ye ,  Mei Sheng Zhou

发明人： Bo Yu ,  Qing Hua Zhong ,  Jian Hui Ye ,  Mei Sheng Zhou

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76232 ,  Y10S148/05 ,  Y10S148/161 ,  Y10S438/978

摘要： A method for forming insulator filled, shallow trench isolation regions, with rounded corners, has been developed. The process features the use of a polymer coated opening, in an insulator layer, used as a mask to define the shallow trench region in silicon. After completion of the shallow trench formation the polymer spacers are removed, exposing a region of unetched semiconductor, that had been protected by the polymer spacers, during the shallow trench dry etching procedure. The sharp corner, at the intersection between the shallow trench and the unetched region of semiconductor, is then converted to a rounded corner, via thermal oxidation of exposed silicon surfaces. The polymer spacers also eliminate the top corner wraparound.

摘要翻译： 已经开发了用于形成具有圆角的绝缘体填充的浅沟槽隔离区域的方法。 该方法的特征在于在绝缘体层中使用聚合物涂布的开口，用作掩模以限定硅中的浅沟槽区域。 在浅沟槽形成完成之后，去除聚合物间隔物，暴露在浅沟槽干法蚀刻过程中被聚合物间隔物保护的未蚀刻半导体区域。 然后，通过暴露的硅表面的热氧化，在浅沟槽和半导体的未蚀刻区域之间的交叉点处的尖角被转换成圆角。 聚合物间隔物也消除了顶角环绕​​。

公开(公告)号：US08415236B2

公开(公告)日：2013-04-09

申请号：US12648309

申请日：2009-12-29

申请人： Han Guan Chew ,  Jinping Liu ,  Alex Kai Hung See ,  Mei Sheng Zhou

发明人： Han Guan Chew ,  Jinping Liu ,  Alex Kai Hung See ,  Mei Sheng Zhou

IPC分类号： H01L21/20

CPC分类号： H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/7848

摘要： A method for fabricating a semiconductor device is provided. The method comprises selectively forming a first layer over a first and second exposed portions of a substrate. The first and second exposed portions are of different sizes and are located adjacent to a first and second active devices. During the first layer formation, a gas mixture comprising first and second source gases that function as growth components for forming the first layer and a reactant gas that functions as an etching component for controlling selectivity of the first layer growth is provided. The reactant gas is different from the first and second source gases and one of first and second source gases forms the first layer at a faster rate over the first exposed portion as compared to the second exposed portion and the other source gas exhibits an opposite behavior.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括在衬底的第一和第二暴露部分上选择性地形成第一层。 第一和第二暴露部分具有不同的尺寸并且位于第一和第二有源器件附近。 在第一层形成期间，提供了包含用作形成第一层的生长组分的第一和第二源气体和用作控制第一层生长选择性的蚀刻组分的反应气体的气体混合物。 反应物气体与第一和第二源气体不同，并且第一和第二源气体之一与第二暴露部分相比以较快的速率在第一暴露部分上形成第一层，而另一个源气体表现出相反的作用。

公开(公告)号：US08354347B2

公开(公告)日：2013-01-15

申请号：US11953881

申请日：2007-12-11

申请人： Jianhui Ye ,  Huang Liu ,  Alex K H See ,  Wei Lu ,  Chun Hui Low ,  Chim Seng Seet ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： Jianhui Ye ,  Huang Liu ,  Alex K H See ,  Wei Lu ,  Chun Hui Low ,  Chim Seng Seet ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L21/461

CPC分类号： H01L21/76832 ,  H01L21/76895 ,  H01L21/76897

摘要： A composite etch stop layer which comprises primary and secondary stop layers is used to form contacts in a dielectric layer to contact regions in a substrate. The secondary etch stop layer includes a high-k dielectric material to achieve high etch selectivity with the dielectric layer during contact formation. The secondary stop layer is removed to expose the contact regions. Removal of the secondary stop layer is achieved with high selectivity to the materials therebelow.

公开(公告)号：US08293544B2

公开(公告)日：2012-10-23

申请号：US12220792

申请日：2008-07-28

申请人： Debora Chyiu Hyia Poon ,  Alex Kh See ,  Francis Benistant ,  Benjamin Colombeau ,  Yun Ling Tan ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： Debora Chyiu Hyia Poon ,  Alex Kh See ,  Francis Benistant ,  Benjamin Colombeau ,  Yun Ling Tan ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L21/00

CPC分类号： H01L27/088 ,  H01L27/0211

摘要： A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.

摘要翻译： 制造半导体器件的方法（和半导体器件）利用热接近校正（TPC）技术来减少退火期间热变化的影响。 在实际制造之前，确定集成电路设计中感兴趣的位置（例如，晶体管），并且定义该位置周围的有效热区。 用于在该区域内制造的结构的热性质被用于计算在给定的退火过程中在感兴趣的位置将实现的估计温度。 如果估计温度低于或高于预定目标温度（或范围），则执行TPC。 可以执行各种TPC技术，例如在感兴趣的位置添加虚拟单元和/或改变要制造的结构的尺寸（导致经修改的热校正设计，以抑制由热变化引起的器件性能的局部变化 在退火期间。