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    SEMICONDUCTOR DEVICE
    62.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20080135926A1

    公开(公告)日：2008-06-12

    申请号：US11936412

    申请日：2007-11-07

    申请人： Syotaro Ono ,  Wataru Saito ,  Masakatsu Takashita ,  Yasuto Sumi ,  Masaru Izumisawa ,  Hiroshi Ohta

    发明人： Syotaro Ono ,  Wataru Saito ,  Masakatsu Takashita ,  Yasuto Sumi ,  Masaru Izumisawa ,  Hiroshi Ohta

    IPC分类号： H01L27/06

    CPC分类号： H01L29/7811 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095

    摘要： A semiconductor device includes: a drift layer having a superjunction structure; a semiconductor base layer selectively formed in a part of one surface of the drift layer; a first RESURF layer formed around a region having the semiconductor base layer formed thereon; a second semiconductor RESURF layer of a conductivity type which is opposite to a conductivity type of the first semiconductor RESURF layer; a first main electrode connected to a first surface of the drift layer; and a second main electrode connected to a second surface of the drift layer. The first RESURF layer is connected to the semiconductor base layer. The second semiconductor RESURF layer is in contact with the first semiconductor RESURF layer.

    摘要翻译： 一种半导体器件包括：具有超结构结构的漂移层; 选择性地形成在所述漂移层的一个表面的一部分中的半导体基层; 在其上形成有半导体基底层的区域周围形成的第一RESURF层; 与第一半导体RESURF层的导电类型相反的导电类型的第二半导体RESURF层; 连接到所述漂移层的第一表面的第一主电极; 以及连接到漂移层的第二表面的第二主电极。 第一RESURF层连接到半导体基层。 第二半导体RESURF层与第一半导体RESURF层接触。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    63.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20070267664A1

    公开(公告)日：2007-11-22

    申请号：US11751244

    申请日：2007-05-21

    申请人： Yasuto SUMI ,  Masakatsu Takashita ,  Masaru Izumisawa ,  Hiroshi Ohta ,  Wataru Saito ,  Syotaro Ono

    发明人： Yasuto SUMI ,  Masakatsu Takashita ,  Masaru Izumisawa ,  Hiroshi Ohta ,  Wataru Saito ,  Syotaro Ono

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7802 ,  H01L21/26586 ,  H01L23/544 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device according to the present invention comprises a first semiconductor layer of the first conductivity type. A pillar layer includes first semiconductor pillars of the first conductivity type and second semiconductor pillars of the second conductivity type arranged periodically and alternately on the first semiconductor layer. The first and second semiconductor pillar layer have a cross section in the shape of stripes in a planar direction. There is a semiconductor base layer of the second conductivity type selectively formed in a surface of the second semiconductor pillar, and a semiconductor diffusion layer of the first conductivity type selectively formed in a surface of the semiconductor base layer. The longitudinal direction of the shape of stripes is made almost same as the direction of pattern shift caused in the first semiconductor layer.

    摘要翻译： 根据本发明的半导体器件包括第一导电类型的第一半导体层。 柱层包括第一导电类型的第一半导体柱和第二导电类型的第二半导体柱，其周期性和交替地布置在第一半导体层上。 第一和第二半导体柱层在平面方向上具有条状的横截面。 存在选择性地形成在第二半导体柱的表面中的第二导电类型的半导体基底层和选择性地形成在半导体基底层的表面中的第一导电类型的半导体扩散层。 条纹形状的纵向方向与第一半导体层中引起的图案偏移的方向几乎相同。

    NITRIDE SEMICONDUCTOR DEVICE
    64.
    发明申请
    NITRIDE SEMICONDUCTOR DEVICE 失效
    氮化物半导体器件

    公开(公告)号：US20070241337A1

    公开(公告)日：2007-10-18

    申请号：US11766484

    申请日：2007-06-21

    申请人： Wataru Saito ,  Ichiro Omura

    发明人： Wataru Saito ,  Ichiro Omura

    IPC分类号： H01L29/94

    CPC分类号： H01L29/66462 ,  H01L29/0692 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/7786

    摘要： In a nitride semiconductor device according to one embodiment of the invention, a p-type gallium nitride (GaN) layer electrically connected to a source electrode and extending and projecting to a drain electrode side with respect to a gate electrode is formed on an undoped or n-type aluminum gallium nitride (AlGaN) layer serving as a barrier layer.

    摘要翻译： 在根据本发明的一个实施方案的氮化物半导体器件中，在未掺杂的或未掺杂的或未掺杂的氮化物半导体器件上形成电连接到源电极并相对于栅电极延伸并突出到漏极侧的p型氮化镓（GaN） n型氮化镓铝（AlGaN）层作为阻挡层。

    Power semiconductor device
    65.
    发明授权
    Power semiconductor device 有权
    功率半导体器件

    公开(公告)号：US07276773B2

    公开(公告)日：2007-10-02

    申请号：US11117342

    申请日：2005-04-29

    申请人： Wataru Saito ,  Ichiro Omura

    发明人： Wataru Saito ,  Ichiro Omura

    IPC分类号： H01L29/72

    CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0878 ,  H01L29/7397 ,  H01L29/872

    摘要： A power semiconductor device includes second semiconductor layers of a first conductivity type and third semiconductor layers of a second conductivity type alternately disposed on a first semiconductor layer of the first conductivity type. The device further includes fourth semiconductor layers of the second conductivity type disposed in contact with upper portions of the third semiconductor layers between the second semiconductor layers, and fifth semiconductor layers of the first conductivity type formed in surfaces of the fourth semiconductor layers. The first semiconductor layer is lower in impurity concentration of the first conductivity type than each second semiconductor layer. The third semiconductor layer includes a fundamental portion and an impurity-amount-larger portion formed locally in a depth direction and higher in impurity amount than the fundamental portion. The impurity amount is defined by a total amount of impurities of the second conductivity type over a cross section in a lateral direction.

    摘要翻译： 功率半导体器件包括交替设置在第一导电类型的第一半导体层上的第一导电类型的第二半导体层和第二导电类型的第三半导体层。 该器件还包括第二导电类型的第四半导体层，与第二半导体层之间的第三半导体层的上部接触，以及形成在第四半导体层的表面中的第一导电类型的第五半导体层。 第一半导体层的第一导电类型的杂质浓度比每个第二半导体层低。 第三半导体层包括基本部分和在深度方向上局部形成的杂质量较大部分，并且杂质量高于基本部分。 杂质量由横向横截面上的第二导电类型的杂质的总量限定。

    SEMICONDUCTOR DEVICE
    66.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20070114602A1

    公开(公告)日：2007-05-24

    申请号：US11562708

    申请日：2006-11-22

    申请人： Wataru Saito ,  Ichiro Omura

    发明人： Wataru Saito ,  Ichiro Omura

    IPC分类号： H01L29/94

    CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7811

    摘要： A semiconductor device includes: a first semiconductor layer of a first conductivity type; a first semiconductor region of the first conductivity type and a second semiconductor region of a second conductivity type alternately arranged in a lateral direction on the first semiconductor layer of the first conductivity type; a third semiconductor region of the second conductivity type formed on the first semiconductor region; a fourth semiconductor region of the first conductivity type formed on a portion of the surface of the third semiconductor region; a control electrode provided via an first insulating film in a groove formed in contact with the fourth semiconductor region, the third semiconductor region, and the first semiconductor region; a first main electrode electrically connected to the first semiconductor layer; a second main electrode forming a junction with the third and fourth semiconductor region; and a fifth semiconductor region of the second conductivity type. The fifth semiconductor region is formed in contact with the first insulating film, the first semiconductor region, and the second semiconductor region. The bottom face of the fifth semiconductor region is deeper than the bottom face of the control electrode. Alternatively, the fifth semiconductor region may be spaced apart from the first insulating film.

    摘要翻译： 半导体器件包括：第一导电类型的第一半导体层; 第一导电类型的第一半导体区域和在第一导电类型的第一半导体层上沿横向交替布置的第二导电类型的第二半导体区域; 形成在第一半导体区域上的第二导电类型的第三半导体区域; 形成在第三半导体区域的表面的一部分上的第一导电类型的第四半导体区域; 在与所述第四半导体区域，所述第三半导体区域和所述第一半导体区域接触形成的沟槽中经由第一绝缘膜设置的控制电极; 电连接到第一半导体层的第一主电极; 形成与第三和第四半导体区域的结的第二主电极; 和第二导电类型的第五半导体区域。 第五半导体区域形成为与第一绝缘膜，第一半导体区域和第二半导体区域接触。 第五半导体区域的底面比控制电极的底面更深。 或者，第五半导体区域可以与第一绝缘膜间隔开。

    Semiconductor element and method of manufacturing the same
    67.
    发明申请
    Semiconductor element and method of manufacturing the same 失效
    半导体元件及其制造方法

    公开(公告)号：US20070018243A1

    公开(公告)日：2007-01-25

    申请号：US11485284

    申请日：2006-07-13

    申请人： Syotaro Ono ,  Wataru Saito ,  Yusuke Kawaguchi ,  Yoshihiro Yamaguchi

    发明人： Syotaro Ono ,  Wataru Saito ,  Yusuke Kawaguchi ,  Yoshihiro Yamaguchi

    IPC分类号： H01L29/94 ,  H01L21/336

    CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/66727 ,  H01L29/66734

    摘要： A semiconductor element is provided, comprising a first semiconductor layer of the first conduction type; and a pillar layer including first semiconductor pillars of the first conduction type and second semiconductor pillars of the second conduction type arranged periodically and alternately on the first semiconductor layer. A semiconductor base layer of the second conduction type is formed on the upper surface of the pillar layer, And a second semiconductor layer of the first conduction type is formed on the upper surface of the semiconductor base layer. A control electrode of the trench gate type is formed in a trench, which is formed in depth through the semiconductor base layer to the first semiconductor pillar. The control electrode is tapered such that the width thereof decreases with the distance from a second main electrode toward a first main electrode and the tip thereof locates almost at the center of the first semiconductor pillar.

    摘要翻译： 提供一种半导体元件，包括第一导电类型的第一半导体层; 以及第一导电型的第一半导体柱和第二导电型的第二半导体柱在第一半导体层上周期性且交替地配置的柱层。 第二导电类型的半导体基层形成在柱层的上表面上，第一导电类型的第二半导体层形成在半导体基层的上表面上。 沟槽栅型的控制电极形成在沟槽中，该沟槽通过半导体基底层向第一半导体柱形成深度。 控制电极是锥形的，使得其宽度随着从第二主电极朝向第一主电极的距离而减小，并且其尖端几乎位于第一半导体柱的中心。

    Nitride semiconductor device
    68.
    发明申请
    Nitride semiconductor device 失效
    氮化物半导体器件

    公开(公告)号：US20060170003A1

    公开(公告)日：2006-08-03

    申请号：US11149208

    申请日：2005-06-10

    申请人： Wataru Saito ,  Ichiro Omura ,  Kouhei Morizuka

    发明人： Wataru Saito ,  Ichiro Omura ,  Kouhei Morizuka

    IPC分类号： H01L31/109

    CPC分类号： H01L29/7787 ,  H01L29/0649 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/66462

    摘要： A multi-layered structure in which a p-3C-SiC layer 102 is formed above a p-Si substrate 101 is formed, above which an I-GaN layer (channel layer) 103, an n-AlGaN layer (barrier layer) 104 are formed. A source electrode 201, a drain electrode 202, and a gate electrode 203 are formed above the n-AlGaN layer 104. The source electrode 201 and the drain electrode 202 form an ohmic contact with the n-AlGaN layer 104. The gate electrode 203 forms a Schottky junction with the n-AlGaN layer 104.

    摘要翻译： 形成在p-Si衬底101上形成p-3C-SiC层102的多层结构，其中I-GaN层（沟道层）103，n-AlGaN层（势垒层）104 形成。 源极电极201，漏极电极202和栅电极203形成在n-AlGaN层104的上方。 源电极201和漏电极202与n-AlGaN层104形成欧姆接触。 栅电极203与n-AlGaN层104形成肖特基结。