公开(公告)号：US08045412B2

公开(公告)日：2011-10-25

申请号：US12487165

申请日：2009-06-18

申请人： Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Andrew John Carter ,  Daniel Reed

发明人： Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Andrew John Carter ,  Daniel Reed

IPC分类号： G11C7/00

CPC分类号： G11C13/0064 ,  G11C11/1675 ,  G11C11/56 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0088 ,  G11C2211/5622 ,  G11C2211/5642 ,  G11C2211/5643 ,  G11C2213/79

摘要： Apparatus and associated method for transferring data to memory, such as resistive sense memory (RSM). In accordance with some embodiments, input data comprising a sequence of logical states are transferred to a block of memory by concurrently writing a first logical state from the sequence to each of a first plurality of unit cells during a first write step, and concurrently writing a second logical state from the sequence to each of a second non-overlapping plurality of unit cells during a second write step.

摘要翻译： 用于将数据传送到存储器的装置和相关方法，例如电阻读出存储器（RSM）。 根据一些实施例，包括逻辑状态序列的输入数据通过在第一写入步骤期间同时向第一多个单位单元中的每个单元写入第一逻辑状态而将第一逻辑状态写入存储器块，并且同时写入 在第二写入步骤期间从序列到第二非重叠多个单位单元中的每一个的第二逻辑状态。

公开(公告)号：US20100302849A1

公开(公告)日：2010-12-02

申请号：US12474463

申请日：2009-05-29

申请人： Chulmin Jung ,  Harry Hongyue Liu ,  Brian Lee ,  Yong Lu ,  Dadi Setiadi

发明人： Chulmin Jung ,  Harry Hongyue Liu ,  Brian Lee ,  Yong Lu ,  Dadi Setiadi

IPC分类号： G11C14/00 ,  G11C16/04

CPC分类号： G11C11/005 ,  G11C16/26 ,  G11C2216/14

摘要： Method and apparatus for outputting data from a memory array having a plurality of non-volatile memory cells arranged into rows and columns. In accordance with various embodiments, charge is stored in a volatile memory cell connected to the memory array, and the stored charge is subsequently discharged from the volatile memory cell through a selected column. In some embodiments, the volatile memory cell is a dynamic random access memory (DRAM) cell from a row of said cells with each DRAM cell along the row coupled to a respective column in the memory array, and each column of non-volatile memory cells comprises Flash memory cells connected in a NAND configuration.

摘要翻译： 用于从具有排列成行和列的多个非易失性存储单元的存储器阵列输出数据的方法和装置。 根据各种实施例，电荷被存储在连接到存储器阵列的易失性存储单元中，并且随后通过所选择的列从易失性存储器单元中释放存储的电荷。 在一些实施例中，易失性存储器单元是来自所述单元的行的动态随机存取存储器（DRAM）单元，其中每个DRAM单元沿着与存储器阵列中的相应列耦合的行，并且每列非易失性存储单元 包括以NAND配置连接的闪存单元。

公开(公告)号：US08363449B2

公开(公告)日：2013-01-29

申请号：US13206550

申请日：2011-08-10

申请人： Chulmin Jung ,  Yong Lu ,  Harry Hongyue Liu

发明人： Chulmin Jung ,  Yong Lu ,  Harry Hongyue Liu

IPC分类号： G11C11/00

CPC分类号： G11C13/0002 ,  G11C7/12 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0069

摘要： A method and apparatus for writing data to a non-volatile memory cell, such as an STRAM memory cell or an RRAM memory cell. In some embodiments, a plurality of N non-volatile memory cells, where N is a greater than two, are connected to a common floating source line. A write circuit is adapted to program a selected memory cell of the plurality to a selected data state by passing a write current of selected magnitude through the selected memory cell and concurrently passing a portion of the write current in parallel through each of the remaining N−1 memory cells of the plurality via the common floating source line.

摘要翻译： 用于将数据写入诸如STRAM存储器单元或RRAM存储器单元的非易失性存储单元的方法和装置。 在一些实施例中，其中N大于2的多个N个非易失性存储器单元连接到公共的浮动源线。 写入电路适于通过将所选择的大小的写入电流通过所选择的存储器单元来编程所选择的数据状态的所选择的存储单元，并且并行地通过所述剩余的N- 1个存储单元经由公共浮动源线。

公开(公告)号：US08004872B2

公开(公告)日：2011-08-23

申请号：US12272507

申请日：2008-11-17

申请人： Chulmin Jung ,  Yong Lu ,  Harry Hongyue Liu

发明人： Chulmin Jung ,  Yong Lu ,  Harry Hongyue Liu

IPC分类号： G11C11/10

CPC分类号： G11C13/0002 ,  G11C7/12 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0069

摘要： A method and apparatus for writing data to a non-volatile memory cell, such as an RRAM memory cell. In some embodiments, a semiconductor array of non-volatile memory cells comprises a resistive sense element (RSE) and a switching device. A RSE of a plurality of memory cells is connected to a bit line while the switching device of a plurality of memory cells is connected to a word line and operated to select a memory cell. A source line is connected to the switching device and connects a series of memory cells together. Further, a driver circuit is connected to the bit line and writes a selected RSE of a selected source line to a selected resistive state by passing a write current along a write current path that passes through the selected RSE and through at least a portion of the remaining RSE connected to the selected source line.

摘要翻译： 一种将数据写入诸如RRAM存储单元的非易失性存储单元的方法和装置。 在一些实施例中，非易失性存储单元的半导体阵列包括电阻感测元件（RSE）和开关器件。 多个存储单元的RSE连接到位线，而多个存储单元的开关器件连接到字线并被操作以选择存储器单元。 源极线连接到开关器件，并将一系列存储器单元连接在一起。 此外，驱动器电路连接到位线，并且通过使写入电流沿着通过所选择的RSE的写入电流路径并且通过至少一部分所述选择的RSE而将所选择的源极线的选定RSE写入所选择的电阻状态 剩余的RSE连接到所选择的源线。

公开(公告)号：US07830708B1

公开(公告)日：2010-11-09

申请号：US12428002

申请日：2009-04-22

申请人： Chulmin Jung ,  Yong Lu ,  Harry Hongyue Liu

发明人： Chulmin Jung ,  Yong Lu ,  Harry Hongyue Liu

IPC分类号： G11C16/00

CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C2211/5631 ,  G11C2211/5632

摘要： Method and apparatus for compensating for variations in memory cell programmed state distributions, such as but not limited to a non-volatile memory formed of NAND configured Flash memory cells. In accordance with various embodiments, a memory block is formed from a plurality of memory cells that are arranged into rows and columns within the memory block, each memory cell configured to have a programmed state. A selected row of the memory block is read by concurrently applying a stepped sequence of threshold voltages to each memory cell along the selected row while sequentially decoupling read current from groups of memory cells along the selected row as the programmed states of said groups of cells are successively determined.

摘要翻译： 用于补偿存储器单元编程状态分布的变化的方法和装置，例如但不限于由NAND配置的闪存单元形成的非易失性存储器。 根据各种实施例，存储器块由多个存储器单元形成，多个存储器单元被布置成存储器块内的行和列，每个存储器单元被配置为具有编程状态。 存储器块的选定行通过沿着所选择的行并行地向每个存储器单元施加阶梯式序列来读取，同时沿着所选行的顺序地将读取电流与存储器单元组分离，因为所述单元组的编程状态为 先后确定。

公开(公告)号：US08363450B2

公开(公告)日：2013-01-29

申请号：US13280109

申请日：2011-10-24

申请人： Chulmin Jung ,  Yong Lu ,  Insik Jin ,  YoungPil Kim ,  Harry Hongyue Liu

发明人： Chulmin Jung ,  Yong Lu ,  Insik Jin ,  YoungPil Kim ,  Harry Hongyue Liu

IPC分类号： G11C11/00

CPC分类号： A01H6/14 ,  A01H5/02

摘要： A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns. A selection circuit is provided that is capable of activating the first block of memory cells while deactivating the second block of memory cells. Further, a read circuit is provided that is capable of reading a logical state of a predetermined memory cell in the first block of memory cells with a reduced leak current by programming a first resistive state to the block selection elements corresponding to the first block of memory cells while programming a second resistive state to the block selection elements corresponding to the second block of memory cells.

摘要翻译： 一种用于从非易失性存储单元读取数据的方法和装置。 在一些实施例中，非易失性存储器单元的交叉点阵列被布置成行和列。 提供了选择电路，其能够在禁用第二存储单元块的同时激活存储器单元的第一块。 此外，提供一种读取电路，其能够通过对与第一存储器块相对应的块选择元件编程第一电阻状态，以减小的漏电流来读取存储器单元的第一块中的预定存储器单元的逻辑状态 同时将第二电阻状态编程到对应于存储器单元的第二块的块选择元件。

公开(公告)号：US08098507B2

公开(公告)日：2012-01-17

申请号：US12502199

申请日：2009-07-13

申请人： Chulmin Jung ,  Yong Lu ,  Insik Jin ,  YoungPil Kim ,  Harry Hongyue Liu

发明人： Chulmin Jung ,  Yong Lu ,  Insik Jin ,  YoungPil Kim ,  Harry Hongyue Liu

IPC分类号： G11C11/00

CPC分类号： G11C13/003 ,  G11C2213/76 ,  G11C2213/77 ,  G11C2213/78 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1266 ,  H01L45/147

摘要： A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns. A selection circuit is provided that is capable of activating the first block of memory cells while deactivating the second block of memory cells. Further, a read circuit is provided that is capable of reading a logical state of a predetermined memory cell in the first block of memory cells with a reduced leak current by programming a first resistive state to the block selection elements corresponding to the first block of memory cells while programming a second resistive state to the block selection elements corresponding to the second block of memory cells.

摘要翻译： 一种用于从非易失性存储单元读取数据的方法和装置。 在一些实施例中，非易失性存储器单元的交叉点阵列被布置成行和列。 提供了选择电路，其能够在禁用第二存储单元块的同时激活存储器单元的第一块。 此外，提供一种读取电路，其能够通过对与第一存储器块相对应的块选择元件编程第一电阻状态，以减小的漏电流来读取存储器单元的第一块中的预定存储器单元的逻辑状态 同时将第二电阻状态编程到对应于存储器单元的第二块的块选择元件。

公开(公告)号：US07881095B2

公开(公告)日：2011-02-01

申请号：US12269630

申请日：2008-11-12

申请人： Yong Lu ,  Harry Hongyue Liu

发明人： Yong Lu ,  Harry Hongyue Liu

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2213/32 ,  G11C2213/79

摘要： Apparatus and associated method for asymmetric write current compensation for resistive sense memory (RSM) cells, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) cells. In accordance with some embodiments, an RSM cell includes an RSM element coupled to a switching device. The switching device has a plurality of terminals. A control circuit compensates for asymmetric write characteristics of the RSM cell by limiting a range of voltage differentials across the terminals so as to be equal to or less than a magnitude of a source voltage applied to the switching device, thereby providing bi-directional write currents of substantially equal magnitude through the RSM element.

摘要翻译： 用于电阻感测存储器（RSM）单元的非对称写入电流补偿的装置和相关方法，例如但不限于自旋转矩传递随机存取存储器（STRAM）或电阻随机存取存储器（RRAM）单元。 根据一些实施例，RSM单元包括耦合到开关装置的RSM元件。 开关装置具有多个端子。 控制电路通过限制端子两端的电压差的范围来补偿RSM单元的不对称写入特性，以便等于或小于施加到开关器件的源极电压的幅度，由此提供双向写入电流 通过RSM元件具有基本相等的幅度。

公开(公告)号：US20110007548A1

公开(公告)日：2011-01-13

申请号：US12502199

申请日：2009-07-13

申请人： Chulmin Jung ,  Yong Lu ,  Insik Jin ,  YoungPil Kim ,  Harry Hongyue Liu

发明人： Chulmin Jung ,  Yong Lu ,  Insik Jin ,  YoungPil Kim ,  Harry Hongyue Liu

IPC分类号： G11C11/00 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C13/003 ,  G11C2213/76 ,  G11C2213/77 ,  G11C2213/78 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1266 ,  H01L45/147

摘要： A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns. A selection circuit is provided that is capable of activating the first block of memory cells while deactivating the second block of memory cells. Further, a read circuit is provided that is capable of reading a logical state of a predetermined memory cell in the first block of memory cells with a reduced leak current by programming a first resistive state to the block selection elements corresponding to the first block of memory cells while programming a second resistive state to the block selection elements corresponding to the second block of memory cells.

摘要翻译： 一种用于从非易失性存储单元读取数据的方法和装置。 在一些实施例中，非易失性存储器单元的交叉点阵列被布置成行和列。 提供了选择电路，其能够在禁用第二存储单元块的同时激活存储器单元的第一块。 此外，提供一种读取电路，其能够通过对与第一存储器块相对应的块选择元件编程第一电阻状态，以减小的漏电流来读取存储器单元的第一块中的预定存储器单元的逻辑状态 同时将第二电阻状态编程到对应于存储器单元的第二块的块选择元件。

公开(公告)号：US20100271875A1

公开(公告)日：2010-10-28

申请号：US12428002

申请日：2009-04-22

申请人： Chulmin Jung ,  Yong Lu ,  Harry Hongyue Liu

发明人： Chulmin Jung ,  Yong Lu ,  Harry Hongyue Liu

IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C2211/5631 ,  G11C2211/5632

摘要： Method and apparatus for compensating for variations in memory cell programmed state distributions, such as but not limited to a non-volatile memory formed of NAND configured Flash memory cells. In accordance with various embodiments, a memory block is formed from a plurality of memory cells that are arranged into rows and columns within the memory block, each memory cell configured to have a programmed state. A selected row of the memory block is read by concurrently applying a stepped sequence of threshold voltages to each memory cell along the selected row while sequentially decoupling read current from groups of memory cells along the selected row as the programmed states of said groups of cells are successively determined.

摘要翻译： 用于补偿存储器单元编程状态分布的变化的方法和装置，例如但不限于由NAND配置的闪存单元形成的非易失性存储器。 根据各种实施例，存储器块由多个存储器单元形成，多个存储器单元被布置成存储器块内的行和列，每个存储器单元被配置为具有编程状态。 存储器块的选定行通过沿着所选择的行并行地向每个存储器单元施加阶梯式序列来读取，同时沿着所选行的顺序地将读取电流与存储器单元组分离，因为所述单元组的编程状态为 先后确定。