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88 条记录 (耗时 0.027 秒)

    Current cancellation for non-volatile memory
    1.
    发明授权
    Current cancellation for non-volatile memory 有权
    当前取消非易失性存储器

    公开(公告)号：US08203894B2

    公开(公告)日：2012-06-19

    申请号：US13081170

    申请日：2011-04-06

    申请人： Chulmin Jung ,  Insik Jin ,  YoungPil Kim ,  Yong Lu ,  Harry Hongyue Liu ,  Andrew John Carter

    发明人： Chulmin Jung ,  Insik Jin ,  YoungPil Kim ,  Yong Lu ,  Harry Hongyue Liu ,  Andrew John Carter

    IPC分类号： G11C7/22

    CPC分类号： G11C11/1673

    摘要： A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns that are each controlled by a line driver. A read circuit is provided that is capable of reading a logical state of a predetermined memory cell by differentiating a non-integrated first reference value from a non-integrated second reference value. Further, each reference value is measured immediately after configuring the column corresponding to the predetermined memory cell to produce a first and second amount of current.

    摘要翻译： 一种用于从非易失性存储单元读取数据的方法和装置。 在一些实施例中，非易失性存储器单元的交叉点阵列被布置成行和列，每个行和列都由线驱动器控制。 提供读取电路，其能够通过将非积分的第一参考值与非积分的第二参考值进行微分来读取预定存储器单元的逻辑状态。 此外，在配置与预定存储单元相对应的列之后立即测量每个参考值以产生第一和第二电流量。

    NAND FLASH MEMORY WITH INTEGRATED BIT LINE CAPACITANCE
    4.
    发明申请
    NAND FLASH MEMORY WITH INTEGRATED BIT LINE CAPACITANCE 有权
    具有集成位线电容的NAND闪存

    公开(公告)号：US20100302849A1

    公开(公告)日：2010-12-02

    申请号：US12474463

    申请日：2009-05-29

    申请人： Chulmin Jung ,  Harry Hongyue Liu ,  Brian Lee ,  Yong Lu ,  Dadi Setiadi

    发明人： Chulmin Jung ,  Harry Hongyue Liu ,  Brian Lee ,  Yong Lu ,  Dadi Setiadi

    IPC分类号： G11C14/00 ,  G11C16/04

    CPC分类号： G11C11/005 ,  G11C16/26 ,  G11C2216/14

    摘要： Method and apparatus for outputting data from a memory array having a plurality of non-volatile memory cells arranged into rows and columns. In accordance with various embodiments, charge is stored in a volatile memory cell connected to the memory array, and the stored charge is subsequently discharged from the volatile memory cell through a selected column. In some embodiments, the volatile memory cell is a dynamic random access memory (DRAM) cell from a row of said cells with each DRAM cell along the row coupled to a respective column in the memory array, and each column of non-volatile memory cells comprises Flash memory cells connected in a NAND configuration.

    摘要翻译： 用于从具有排列成行和列的多个非易失性存储单元的存储器阵列输出数据的方法和装置。 根据各种实施例，电荷被存储在连接到存储器阵列的易失性存储单元中，并且随后通过所选择的列从易失性存储器单元中释放存储的电荷。 在一些实施例中，易失性存储器单元是来自所述单元的行的动态随机存取存储器（DRAM）单元，其中每个DRAM单元沿着与存储器阵列中的相应列耦合的行，并且每列非易失性存储单元 包括以NAND配置连接的闪存单元。

    COMPUTER MEMORY DEVICE WITH MULTIPLE INTERFACES
    5.
    发明申请
    COMPUTER MEMORY DEVICE WITH MULTIPLE INTERFACES 有权
    具有多个接口的计算机存储器件

    公开(公告)号：US20100177562A1

    公开(公告)日：2010-07-15

    申请号：US12352713

    申请日：2009-01-13

    申请人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Rod V. Bowman

    发明人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Rod V. Bowman

    IPC分类号： G11C11/14 ,  G11C7/00

    CPC分类号： G11C11/22

    摘要： Various embodiments are generally directed to a method and apparatus associated with operating a first memory device with multiple interfaces and a status register. In some embodiments, a first interface is engaged by a host. A memory device that has a plurality of memory cells comprised of at least a magnetic tunneling junction and a spin polarizing magnetic material is connected to a second interface. A status register is maintained by logging at least an error or busy signal during data transfer operations through the first and second interfaces.

    摘要翻译： 各种实施例通常涉及与操作具有多个接口和状态寄存器的第一存储器件相关联的方法和装置。 在一些实施例中，主机接合第一接口。 具有由至少磁性隧道结和自旋极化磁性材料构成的多个存储单元的存储器件连接到第二接口。 通过在数据传输操作期间通过第一和第二接口记录至少一个错误或忙信号来维护状态寄存器。

    Floating source line architecture for non-volatile memory
    6.
    发明授权
    Floating source line architecture for non-volatile memory 有权
    用于非易失性存储器的浮动源线架构

    公开(公告)号：US08363449B2

    公开(公告)日：2013-01-29

    申请号：US13206550

    申请日：2011-08-10

    申请人： Chulmin Jung ,  Yong Lu ,  Harry Hongyue Liu

    发明人： Chulmin Jung ,  Yong Lu ,  Harry Hongyue Liu

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0002 ,  G11C7/12 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0069

    摘要： A method and apparatus for writing data to a non-volatile memory cell, such as an STRAM memory cell or an RRAM memory cell. In some embodiments, a plurality of N non-volatile memory cells, where N is a greater than two, are connected to a common floating source line. A write circuit is adapted to program a selected memory cell of the plurality to a selected data state by passing a write current of selected magnitude through the selected memory cell and concurrently passing a portion of the write current in parallel through each of the remaining N−1 memory cells of the plurality via the common floating source line.

    摘要翻译： 用于将数据写入诸如STRAM存储器单元或RRAM存储器单元的非易失性存储单元的方法和装置。 在一些实施例中，其中N大于2的多个N个非易失性存储器单元连接到公共的浮动源线。 写入电路适于通过将所选择的大小的写入电流通过所选择的存储器单元来编程所选择的数据状态的所选择的存储单元，并且并行地通过所述剩余的N- 1个存储单元经由公共浮动源线。

    Floating source line architecture for non-volatile memory
    7.
    发明授权
    Floating source line architecture for non-volatile memory 有权
    用于非易失性存储器的浮动源线架构

    公开(公告)号：US08004872B2

    公开(公告)日：2011-08-23

    申请号：US12272507

    申请日：2008-11-17

    申请人： Chulmin Jung ,  Yong Lu ,  Harry Hongyue Liu

    发明人： Chulmin Jung ,  Yong Lu ,  Harry Hongyue Liu

    IPC分类号： G11C11/10

    CPC分类号： G11C13/0002 ,  G11C7/12 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0069

    摘要： A method and apparatus for writing data to a non-volatile memory cell, such as an RRAM memory cell. In some embodiments, a semiconductor array of non-volatile memory cells comprises a resistive sense element (RSE) and a switching device. A RSE of a plurality of memory cells is connected to a bit line while the switching device of a plurality of memory cells is connected to a word line and operated to select a memory cell. A source line is connected to the switching device and connects a series of memory cells together. Further, a driver circuit is connected to the bit line and writes a selected RSE of a selected source line to a selected resistive state by passing a write current along a write current path that passes through the selected RSE and through at least a portion of the remaining RSE connected to the selected source line.

    摘要翻译： 一种将数据写入诸如RRAM存储单元的非易失性存储单元的方法和装置。 在一些实施例中，非易失性存储单元的半导体阵列包括电阻感测元件（RSE）和开关器件。 多个存储单元的RSE连接到位线，而多个存储单元的开关器件连接到字线并被操作以选择存储器单元。 源极线连接到开关器件，并将一系列存储器单元连接在一起。 此外，驱动器电路连接到位线，并且通过使写入电流沿着通过所选择的RSE的写入电流路径并且通过至少一部分所述选择的RSE而将所选择的源极线的选定RSE写入所选择的电阻状态 剩余的RSE连接到所选择的源线。

    RESISTIVE SENSE MEMORY ARRAY WITH PARTIAL BLOCK UPDATE CAPABILITY
    10.
    发明申请
    RESISTIVE SENSE MEMORY ARRAY WITH PARTIAL BLOCK UPDATE CAPABILITY 有权
    具有部分块更新能力的电阻式感知存储器阵列

    公开(公告)号：US20110029714A1

    公开(公告)日：2011-02-03

    申请号：US12904653

    申请日：2010-10-14

    申请人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li

    发明人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li

    IPC分类号： G06F12/00 ,  G11C11/21 ,  G11C11/16

    CPC分类号： G11C8/12 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0088 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/79

    摘要： Various embodiments of the present invention are generally directed to a method and apparatus for carrying out a partial block update operation upon a resistive sense memory (RSM) array, such as formed from STRAM or RRAM cells. The RSM array is arranged into multi-cell blocks (sectors), each block having a physical block address (PBA). A first set of user data is written to a selected block at a first PBA. A partial block update operation is performed by writing a second set of user data to a second block at a second PBA, the second set of user data updating a portion of the first set of user data in the first PBA. The first and second blocks are thereafter read to retrieve the second set of user data and a remaining portion of the first set of user data.

    摘要翻译： 本发明的各种实施例总体上涉及一种用于在诸如由STRAM或RRAM单元形成的电阻式感测存储器（RSM）阵列上执行部分块更新操作的方法和装置。 RSM阵列被布置成多小区块（扇区），每个块具有物理块地址（PBA）。 第一组用户数据在第一PBA被写入所选择的块。 通过在第二PBA将第二组用户数据写入第二块来执行部分块更新操作，第二组用户数据更新第一PBA中第一组用户数据的一部分。 然后读取第一和第二块以检索第二组用户数据和第一组用户数据的剩余部分。