公开(公告)号：US06710627B2

公开(公告)日：2004-03-23

申请号：US10322934

申请日：2002-12-18

申请人： Mircea R. Stan ,  Vivek K. De

发明人： Mircea R. Stan ,  Vivek K. De

IPC分类号： H03K19096

CPC分类号： H03K19/0963

摘要： A technique to individually adjust noise immunity of each input of a dynamic circuit including parallel or series-parallel pull-down network includes identifying precharge nodes of the dynamic circuit that require a reduction of noise. The technique further includes identifying NMOS transistor drains connected to respective precharge nodes, and creating a pull-up network of PMOS transistors for the identified precharge nodes. After creating a pull-up network of PMOS transistors, the technique includes arranging the order of the PMOS transistors corresponding to the respective precharge nodes to improve noise immunity and performance of the dynamic circuit. After arranging the order of the PMOS transistors, the technique can further include sizing the PMOS transistors to achieve the required reduction of noise for the precharge nodes.

摘要翻译： 单独调整包括并联或串并联下拉网络的动态电路的每个输入的噪声抗扰度的技术包括识别需要降低噪声的动态电路的预充电节点。 该技术还包括识别连接到相应预充电节点的NMOS晶体管漏极，以及为所识别的预充电节点创建PMOS晶体管的上拉网络。 在创建PMOS晶体管的上拉网络之后，该技术包括布置与各个预充电节点相对应的PMOS晶体管的阶数，以提高动态电路的抗噪声性能和性能。 在布置PMOS晶体管的顺序之后，该技术可以进一步包括对PMOS晶体管进行尺寸调整以实现预充电节点所需的噪声降低。

公开(公告)号：US06643199B1

公开(公告)日：2003-11-04

申请号：US10162929

申请日：2002-06-04

申请人： Stephen H. Tang ,  Steven K. Hsu ,  Vivek K. De ,  Shih-Lien L. Lu

发明人： Stephen H. Tang ,  Steven K. Hsu ,  Vivek K. De ,  Shih-Lien L. Lu

IPC分类号： G11C700

CPC分类号： G11C11/412

摘要： For a memory cell, where an access transistor couples the memory cell to a local bit line, a pMOSFET essentially eliminates sub-threshold leakage current in the access transistor when the memory cell is not being read, and when the memory cell is being read, an additional pMOSFET essentially eliminates sub-threshold leakage current in the access transistor if the memory cell stores an information bit such that it does not discharge the local bit line. In this way, a half-keeper connected to the local bit line does not need to contend with sub-threshold leakage current.

摘要翻译： 对于存储晶体管，其中存取晶体管将存储单元耦合到局部位线，当存储单元未被读取时，pMOSFET基本上消除了存取晶体管中的次阈值泄漏电流，并且当存储单元被读取时， 如果存储单元存储信息位，使得其不释放局部位线，附加的pMOSFET基本上消除了存取晶体管中的次阈值漏电流。 以这种方式，连接到本地位线的半保持器不需要与亚阈值泄漏电流相抗衡。

公开(公告)号：US06642765B2

公开(公告)日：2003-11-04

申请号：US10010046

申请日：2001-12-06

申请人： Dejan Markovic ,  James W. Tschanz ,  Vivek K. De

发明人： Dejan Markovic ,  James W. Tschanz ,  Vivek K. De

IPC分类号： H03K3356

CPC分类号： H03K3/356156 ,  H03K3/0372 ,  H03K3/35625

摘要： Flip-flop circuitry having an input configured to receive an input signal and an output configured to deliver an output signal corresponding to the input signal; a clock terminal configured to provide timing signals for reception of the input signal at the input and transmission of the output signal at the output; two on-path inverters connected serially between the input and output, and configured not to respond to the timing signals; and two feedback inverters respectively connected in parallel with the two on-path inverters, the first and second feedback inverters being configured to respond to the timing signals.

摘要翻译： 触发器电路具有被配置为接收输入信号的输入和被配置为传送对应于输入信号的输出信号的输出; 时钟端子，其被配置为在输出处提供输入和输出输出信号时提供用于接收输入信号的定时信号; 两个通路反相器串联连接在输入和输出之间，并且被配置成不响应定时信号; 以及分别与两个通路反相器并联连接的两个反馈反相器，第一和第二反馈反相器被配置为响应于定时信号。

公开(公告)号：US06567329B2

公开(公告)日：2003-05-20

申请号：US09941053

申请日：2001-08-28

申请人： Dinesh Somasekhar ,  Shih-Lien L. Lu ,  Vivek K. De

发明人： Dinesh Somasekhar ,  Shih-Lien L. Lu ,  Vivek K. De

IPC分类号： G11C702

CPC分类号： G11C11/408 ,  G11C11/4097

摘要： The word-lines and/or bit-lines in a memory are physically arranged to reduce capacitive coupling between signal lines and reference lines. In one embodiment the two bit lines connected to a single sense amplifier are physically separated from each other by bit lines connected to other sense amplifiers. In another embodiment the word-lines are separated from each other by placing them in different metallization layers. In a particular embodiment a single word-line has different portions disposed in different metallization layers.

摘要翻译： 物理地布置存储器中的字线和/或位线以减少信号线和参考线之间的电容耦合。 在一个实施例中，连接到单个读出放大器的两个位线通过连接到其它读出放大器的位线彼此物理分离。 在另一个实施例中，字线通过将它们放置在不同的金属化层中而彼此分离。 在特定实施例中，单个字线具有设置在不同金属化层中的不同部分。

公开(公告)号：US06529045B2

公开(公告)日：2003-03-04

申请号：US09406938

申请日：1999-09-28

申请人： Yibin Ye ,  Reed D. Spotten ,  Vivek K. De

发明人： Yibin Ye ,  Reed D. Spotten ,  Vivek K. De

IPC分类号： H03K19096

CPC分类号： H03K19/0963 ,  H03K19/01728

摘要： A domino logic circuit is provided. The circuit includes an n-channel clock transistor coupled between a dynamic output node and a high voltage connection, with the gate of the clock transistor coupled to receive an inverse clock signal. A first inverter and a second inverter are connected in series such that the input of the first inverter is connected to the output of the second inverter. The input of the second inverter is connected to the dynamic output node. An n-channel level keeper transistor is connected between the dynamic output node and the high voltage connection, and the gate of the level keeper transistor is connected to the output of the first inverter. A pull-down circuit is connected between the dynamic output node and a low-voltage connection.

摘要翻译： 提供多米诺骨牌逻辑电路。 电路包括耦合在动态输出节点和高电压连接之间的n沟道时钟晶体管，时钟晶体管的栅极被耦合以接收反时钟信号。 第一反相器和第二反相器串联连接，使得第一反相器的输入连接到第二反相器的输出。 第二反相器的输入连接到动态输出节点。 N沟道电平保持器晶体管连接在动态输出节点和高压连接之间，电平保持晶体管的栅极连接到第一个反相器的输出端。 下拉电路连接在动态输出节点和低压连接之间。

公开(公告)号：US06519176B1

公开(公告)日：2003-02-11

申请号：US09675579

申请日：2000-09-29

申请人： Fatih Hamzaoglu ,  Ali Keshavarzi ,  Yibin Ye ,  Siva G. Narendra ,  Vivek K. De

发明人： Fatih Hamzaoglu ,  Ali Keshavarzi ,  Yibin Ye ,  Siva G. Narendra ,  Vivek K. De

IPC分类号： G11C1100

CPC分类号： G11C11/412

摘要： A six transistor SRAM cell for single-ended sensing is described along with related memory architecture. The cell comprises a bistable circuit connected to complementary bit lines through a pair of passgate transistors. One of the passgate transistors has a lower threshold voltage than the other transistor. The lower threshold voltage is used to couple the cell to a single-ended sense amplifier through one of the bit lines. In one embodiment fewer than all the bit lines in an array are precharged in order to reduce power consumption in the array.

摘要翻译： 描述了用于单端感测的六晶体管SRAM单元以及相关的存储器架构。 该单元包括通过一对通道晶体管连接到互补位线的双稳态电路。 一个通道晶体管具有比另一个晶体管更低的阈值电压。 较低的阈值电压用于通过其中一条位线将单元耦合到单端读出放大器。 在一个实施例中，少于阵列中的所有位线被预充电以便减少阵列中的功耗。

公开(公告)号：US06411156B1

公开(公告)日：2002-06-25

申请号：US09224575

申请日：1998-12-30

申请人： Shekhar Y. Borkar ,  Vivek K. De ,  Ali Keshavarzi ,  Siva G. Narendra

发明人： Shekhar Y. Borkar ,  Vivek K. De ,  Ali Keshavarzi ,  Siva G. Narendra

IPC分类号： H03K301

CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  H01L27/0928 ,  H01L29/1087 ,  H03K19/00384 ,  H03K19/0948 ,  H03K2217/0018 ,  Y02D10/126 ,  Y02D10/172

摘要： In some embodiments, the invention involves a system including an integrated circuit. The system a circuit including transistors. The system further includes control circuitry to control a setting of a body bias signal to control body biases provided in the circuit to at least partially control a parameter of the integrated circuit, the setting of the body bias signal being responsive to an input signal to the control circuitry. In some embodiments, the invention involves a system including an integrated circuit. The system a circuit including transistors. The system further includes control circuitry to control settings of a body bias signal, a supply voltage signal, and a clock signal to control body biases, supply voltages, and clock frequencies provided in the circuit to at least partially control a parameter of the integrated circuit, the setting of the body bias signal, supply voltage signal, and clock signal being responsive to an input signal to the control circuitry.

摘要翻译： 在一些实施例中，本发明涉及包括集成电路的系统。 该系统包括晶体管的电路。 该系统还包括控制电路，用于控制体偏置信号的设置以控制设置在电路中的身体偏压，以至少部分地控制集成电路的参数，体偏置信号的设置响应于输入信号 控制电路。 在一些实施例中，本发明涉及包括集成电路的系统。 该系统包括晶体管的电路。 该系统还包括控制电路，用于控制体偏置信号，电源电压信号和时钟信号的设置，以控制电路中提供的体偏置，电源电压和时钟频率，以至少部分地控制集成电路的参数 ，所述体偏置信号，电源电压信号和时钟信号的设置响应于控制电路的输入信号。

公开(公告)号：US06300819B1

公开(公告)日：2001-10-09

申请号：US09078395

申请日：1998-05-13

申请人： Vivek K. De ,  Ali Keshavarzi ,  Siva G. Narendra ,  Shekhar Y. Borkar

发明人： Vivek K. De ,  Ali Keshavarzi ,  Siva G. Narendra ,  Shekhar Y. Borkar

IPC分类号： G05F110

CPC分类号： H01L27/0928 ,  H01L29/1087 ,  H03K19/0948

摘要： One embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. Another embodiment of the invention includes a semiconductor circuit including a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors. Still another embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. The circuit also includes a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors.

摘要翻译： 本发明的一个实施例包括一个半导体电路，该半导体电路包括提供接地电压的接地电压节点和具有电耦合到接地电压节点的n型体的pFET晶体管，以使pFET晶体管的偏置正向。 本发明的另一个实施例包括一个半导体电路，其包括提供电源电压的电源电压节点和具有电耦合到电源电压节点的p型体的nFET晶体管，以使nFET晶体管的本体偏置转向。 本发明的另一个实施例包括一个包括接地电压节点以提供接地电压的半导体电路，以及具有电耦合到接地电压节点的n型体的pFET晶体管，以使pFET晶体管的偏置正向。 该电路还包括用于提供电源电压的电源电压节点和具有电耦合到电源电压节点的p型主体的nFET晶体管，以使nFET晶体管的主体偏置转向。

公开(公告)号：US06218892B1

公开(公告)日：2001-04-17

申请号：US09256842

申请日：1999-02-24

申请人： Krishnamurthy Soumyanath ,  Ali Keshavarzi ,  Vivek K. De ,  Shekhar Y. Borkar

发明人： Krishnamurthy Soumyanath ,  Ali Keshavarzi ,  Vivek K. De ,  Shekhar Y. Borkar

IPC分类号： G05F110

CPC分类号： H01L27/0928 ,  H01L29/1087 ,  H03K19/0948 ,  H03L7/0812 ,  H03L7/0995

摘要： In some embodiments, the invention includes circuit having a differential amplifier and body bias control circuitry. The differential amplifier includes a differential pair of first and second FET transistors to at least partially control output voltage signals responsive to input voltage signals, the first and second FET transistors being configured to be matched and having a body. The body bias control circuitry provides a body bias voltage signal to the body to place the first and second FET transistors in a forward body bias condition. The differential amplifier and body bias circuitry may be used in a sense amplifier, comparator, voltage controlled oscillator, delay locked loop, and phase locked loop as well as other circuits.

摘要翻译： 在一些实施例中，本发明包括具有差分放大器和体偏置控制电路的电路。 差分放大器包括第一和第二FET晶体管的差分对，以响应于输入电压信号至少部分地控制输出电压信号，第一和第二FET晶体管被配置为匹配并具有主体。 体偏置控制电路向身体提供体偏置电压信号，以将第一和第二FET晶体管置于正向体偏置状态。 差分放大器和体偏置电路可用于读出放大器，比较器，压控振荡器，延迟锁定环路和锁相环路以及其他电路。

公开(公告)号：US06191606B1

公开(公告)日：2001-02-20

申请号：US09150869

申请日：1998-09-10

申请人： Yibin Ye ,  Vivek K. De

发明人： Yibin Ye ,  Vivek K. De

IPC分类号： H03K1716

CPC分类号： H03K19/0016

摘要： A technique for reducing standby leakage current in a circuit block using input vector activation. A complex circuit includes a plurality of inputs and one or more transistor stacks. At least some of the transistor stacks are coupled to at least one of the inputs. The circuit also includes logic to apply a selected input vector to the plurality of inputs during a standby mode. The input vector is selected based on a configuration of the one or more transistor stacks in the circuit block to turn off a first number of transistors in the transistor stacks. The first number is within a selected percent of a maximum number of transistors in the transistor stacks that can be turned off by any vector applied at the plurality of inputs.

摘要翻译： 一种使用输入向量激活来减少电路块中待机漏电流的技术。 复合电路包括多个输入和一个或多个晶体管堆叠。 至少一些晶体管堆叠被耦合到至少一个输入端。 电路还包括在待机模式期间将所选择的输入矢量应用于多个输入端的逻辑。 基于电路块中的一个或多个晶体管堆叠的配置来选择输入向量，以关闭晶体管堆叠中的第一数量的晶体管。 第一个数字在晶体管堆叠中的最大数量的晶体管的选定百分比之内，可以通过在多个输入端施加的任何矢量来关闭。