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公开(公告)号：US06642765B2
公开(公告)日：2003-11-04
申请号：US10010046
申请日：2001-12-06
Applicant: Dejan Markovic , James W. Tschanz , Vivek K. De
Inventor： Dejan Markovic , James W. Tschanz , Vivek K. De
IPC: H03K3356
CPC classification number: H03K3/356156 , H03K3/0372 , H03K3/35625
Abstract: Flip-flop circuitry having an input configured to receive an input signal and an output configured to deliver an output signal corresponding to the input signal; a clock terminal configured to provide timing signals for reception of the input signal at the input and transmission of the output signal at the output; two on-path inverters connected serially between the input and output, and configured not to respond to the timing signals; and two feedback inverters respectively connected in parallel with the two on-path inverters, the first and second feedback inverters being configured to respond to the timing signals.
Abstract translation: 触发器电路具有被配置为接收输入信号的输入和被配置为传送对应于输入信号的输出信号的输出; 时钟端子，其被配置为在输出处提供输入和输出输出信号时提供用于接收输入信号的定时信号; 两个通路反相器串联连接在输入和输出之间，并且被配置成不响应定时信号; 以及分别与两个通路反相器并联连接的两个反馈反相器，第一和第二反馈反相器被配置为响应于定时信号。
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公开(公告)号：US06970018B2
公开(公告)日：2005-11-29
申请号：US10873243
申请日：2004-06-23
Applicant: Dejan Markovic , James W. Tschanz , Vivek K. De
Inventor： Dejan Markovic , James W. Tschanz , Vivek K. De
IPC: H03K3/012 , H03K3/037 , H03K3/356 , H03K19/094
CPC classification number: H03K3/356113 , H03K3/012 , H03K3/037 , H03K3/356156
Abstract: A cycle latch includes a control circuit which increases the pull-up rate of a storage node by conditionally discharging the feedback node in a cross-coupled inverter keeper structure. The cycle latch includes an NMOS transistor switch for transferring an input value to the storage node, and two more NMOS transistors connected in series for performing the function of the control circuit. By connecting the storage node to a pre-discharged feedback node and then driving the latch with a low-swing clock, improved performance in terms of delay times, energy consumption, and robustness is achieved.
Abstract translation: 循环锁存器包括控制电路，其通过在交叉耦合的逆变器保持器结构中有条件地排放反馈节点来增加存储节点的上拉率。 周期锁存器包括用于将输入值传送到存储节点的NMOS晶体管开关和串联连接的两个NMOS晶体管，用于执行控制电路的功能。 通过将存储节点连接到预放电反馈节点，然后用低摆频时钟驱动锁存器，实现延迟时间，能量消耗和鲁棒性方面的改进的性能。
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公开(公告)号：US06806739B2
公开(公告)日：2004-10-19
申请号：US10330544
申请日：2002-12-30
Applicant: Dejan Markovic , James W. Tschanz , Vivek K. De
Inventor： Dejan Markovic , James W. Tschanz , Vivek K. De
IPC: H03K19094
CPC classification number: H03K3/356113 , H03K3/012 , H03K3/037 , H03K3/356156
Abstract: A cycle latch includes a control circuit which increases the pull-up rate of a storage node by conditionally discharging the feedback node in a cross-coupled inverter keeper structure. The cycle latch includes an NMOS transistor switch for transferring an input value to the storage node, and two more NMOS transistors connected in series for performing the function of the control circuit. By connecting the storage node to a pre-discharged feedback node and then driving the latch with a low-swing clock, improved performance in terms of delay times, energy consumption, and robustness is achieved.
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公开(公告)号：US09484917B2
公开(公告)日：2016-11-01
申请号：US13718372
申请日：2012-12-18
Applicant: Arijit Raychowdhury , Charles Augustine , James W. Tschanz , Vivek K. De
Inventor： Arijit Raychowdhury , Charles Augustine , James W. Tschanz , Vivek K. De
CPC classification number: H03K19/0016 , G05F1/10 , G05F1/461 , G05F1/59 , G06F1/3287 , G06F1/3296 , H03K3/0377 , H03K19/0008
Abstract: Described is an apparatus which comprises: a clamp coupled between a first power supply and a second power supply; and a circuit to operate with the second power supply, wherein the clamp is operable to adjust the second power supply when the apparatus enters a low power mode.
Abstract translation: 描述了一种装置，其包括：耦合在第一电源和第二电源之间的夹具; 以及用于与第二电源操作的电路，其中当所述设备进入低功率模式时，所述钳位器可操作以调节所述第二电源。
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公开(公告)号：US20100219516A1
公开(公告)日：2010-09-02
申请号：US12660305
申请日：2010-02-24
Applicant: Siva G. Narendra , James W. Tschanz , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
Inventor： Siva G. Narendra , James W. Tschanz , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
IPC: H01L23/495
CPC classification number: H01L25/0657 , H01L25/18 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/16145 , H01L2224/16227 , H01L2225/06513 , H01L2225/06527 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
Abstract: An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
Abstract translation: 公开了一种集成电路（IC）封装。 IC封装包括第一裸片; 以及以三维封装布局结合到CPU管芯的第二管芯。
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Patent Agency Ranking
公开(公告)号：US20100145895A1
公开(公告)日：2010-06-10
申请号：US12704789
申请日：2010-02-12
Applicant: Siva G. Narendra , James W. Tschanz , Vivek K. De , Stephen H. Tang
Inventor： Siva G. Narendra , James W. Tschanz , Vivek K. De , Stephen H. Tang
Abstract: A system may include acquisition of a supply voltage information representing past supply voltages supplied to an electrical component, acquisition of a temperature information representing past temperatures of the electrical component, and control of a performance characteristic of the electrical component based on the supply voltage information and the temperature information. Some embodiments may further include determination of a reliability margin based on the supply voltage information, the temperature information, and on a reliability specification of the electrical component, and change of the performance characteristic based on the reliability margin.
Abstract translation: 系统可以包括获取表示提供给电气部件的过去电源电压的电源电压信息，基于电源电压信息获取表示电气部件的过去温度的温度信息和电气部件的性能特性的控制，以及 温度信息。 一些实施例还可以包括基于电源电压信息，温度信息以及电气部件的可靠性规格以及基于可靠性裕度的性能特性的改变来确定可靠性裕度。
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7.发明授权Method, apparatus and system of adjusting one or more performance-related parameters of a processor 有权调整处理器的一个或多个性能相关参数的方法，装置和系统公开(公告)号：US07376849B2
公开(公告)日：2008-05-20
申请号：US10879486
申请日：2004-06-30
Applicant: James W. Tschanz , Stephen H. Tang , Siva G. Narendra , Vivek K. De
Inventor： James W. Tschanz , Stephen H. Tang , Siva G. Narendra , Vivek K. De
IPC: G06F1/00
CPC classification number: G06F1/324 , G06F1/206 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
Abstract: Embodiments of the present invention provide a method, apparatus and system for dynamically adjusting one or more performance-related parameters of a processor core based on at least one operation parameter related to an operating condition of the processor core.
Abstract translation: 本发明的实施例提供了一种用于基于与处理器核心的操作条件相关的至少一个操作参数来动态地调整处理器核心的一个或多个与性能有关的参数的方法，装置和系统。
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公开(公告)号：US07236045B2
公开(公告)日：2007-06-26
申请号：US11038394
申请日：2005-01-21
Applicant: James W. Tschanz , Stephen H. Tang , Victor Zia , Badarinath Kommandur , Siva G. Narendra , Vivek K. De
Inventor： James W. Tschanz , Stephen H. Tang , Victor Zia , Badarinath Kommandur , Siva G. Narendra , Vivek K. De
IPC: G05F1/10
CPC classification number: G05F3/205
Abstract: A bias generator is provided that includes a central bias generator to provide a first bias voltage and a local bias generator to receive the first bias voltage and to provide a second bias voltage. The central bias generator may include a replica bias generator circuit substantially corresponding to the local bias generator.
Abstract translation: 提供偏置发生器，其包括中心偏置发生器以提供第一偏置电压和局部偏置发生器以接收第一偏置电压并提供第二偏置电压。 中心偏置发生器可以包括基本上对应于局部偏置发生器的复制偏压发生器电路。
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9.发明授权Method and apparatus for reducing power consumption through dynamic control of supply voltage and body bias including maintaining a substantially constant operating frequency 有权用于通过动态控制电源电压和身体偏压来降低功耗的方法和装置，包括保持基本恒定的工作频率公开(公告)号：US07120804B2
公开(公告)日：2006-10-10
申请号：US10328573
申请日：2002-12-23
Applicant: James W. Tschanz , Yibin Ye , Liqiong Wei , Vivek K. De
Inventor： James W. Tschanz , Yibin Ye , Liqiong Wei , Vivek K. De
CPC classification number: G06F1/3296 , G06F1/3203 , H03K2217/0018 , Y02D10/126 , Y02D10/172
Abstract: An approach for power reduction of an integrated circuit device. In response to detecting a change in an activity factor associated with an integrated circuit device from a first activity factor to a second activity factor, a supply voltage and a body bias associated with the integrated circuit device are adjusted based on the second activity factor to reduce power consumption. For one aspect, the supply voltage and body bias are adjusted to maintain a substantially constant operating frequency for the integrated circuit device.
Abstract translation: 一种用于集成电路装置的功率降低的方法。 响应于检测到与集成电路器件相关联的活动因素从第一活动因素到第二活动因素的变化，基于第二活动因素来调整与集成电路设备相关联的电源电压和身体偏差以减少 能量消耗。 一方面，调整电源电压和体偏置以保持集成电路器件的基本恒定的工作频率。
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公开(公告)号：US06784688B2
公开(公告)日：2004-08-31
申请号：US10334410
申请日：2002-12-30
Applicant: Muhammad M. Khellah , James W. Tschanz , Yibin Ye , Vivek K. De
Inventor： Muhammad M. Khellah , James W. Tschanz , Yibin Ye , Vivek K. De
IPC: H03K19003
CPC classification number: H04L25/14
Abstract: According to some embodiments, provided are a first signal line, the first signal line coupled to a first repeater, the first repeater to convert a first signal from a received signal level to an output signal level, the first repeater to convert from a first signal level to a second signal level slower than from the second signal level to the first signal level, and a second signal line adjacent to the first signal line, the second signal line coupled to a second repeater adjacent to the first repeater, the second repeater to convert a second signal from a second received signal level to a second output signal level, the second repeater to convert from the first signal level to the second signal level slower than from the second signal level to the first signal level, wherein the received signal level is substantially equivalent to the second output signal level and wherein the second received signal level is substantially equivalent to the output signal level.
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