公开(公告)号：US06628545B1

公开(公告)日：2003-09-30

申请号：US10306080

申请日：2002-11-26

Applicant: Jiang Li ,  Yider Wu ,  Zhizheng Liu

Inventor： Jiang Li ,  Yider Wu ,  Zhizheng Liu

IPC: G11C1604

CPC classification number: G11C16/3404

Abstract: A memory circuit employed in a memory device is disclosed. According to one embodiment, the memory circuit comprises a first memory cell and a second memory cell. The first memory cell has a drain terminal connected to a bit line, which is connected to a sensing circuit. The first memory cell also has a control gate connected to a word line. The second memory cell also has a drain terminal connected to the bit line. The second memory cell has its control gate coupled to ground. The memory circuit supplies a source voltage greater than a ground voltage to a source terminal of the first memory cell and to a source terminal of the second memory cell such that the gate-to-source voltage of the second memory cell is less than the threshold voltage of the second memory cell.

Abstract translation: 公开了一种在存储器件中使用的存储器电路。 根据一个实施例，存储器电路包括第一存储单元和第二存储单元。 第一存储单元具有连接到位线的漏极端子，该位线连接到感测电路。 第一存储单元还具有连接到字线的控制栅极。 第二存储单元还具有连接到位线的漏极端子。 第二存储单元的控制栅极接地。 存储器电路将大于接地电压的源极电压提供给第一存储单元的源极端子和第二存储器单元的源极端子，使得第二存储器单元的栅极 - 源极电压小于阈值 第二存储单元的电压。

公开(公告)号：US06395654B1

公开(公告)日：2002-05-28

申请号：US09648077

申请日：2000-08-25

Applicant: Jean Yang ,  Yider Wu ,  Hidehiko Shiraiwa ,  Mark Ramsbey

Inventor： Jean Yang ,  Yider Wu ,  Hidehiko Shiraiwa ,  Mark Ramsbey

IPC: H01L21225

CPC classification number: H01L29/66833 ,  H01L21/28282 ,  H01L29/792

Abstract: A gate structure for an ONO flash memory device includes a first layer of silicon oxide on top of a semiconductor substrate, a second layer of silicon oxide, a layer of silicon nitride sandwiched between the two silicon oxide layers, and a control gate on top of the second layer of silicon oxide. Nitrogen is implanted into the first layer of silicon oxide and then the semiconductor structure is heated using a rapid thermal tool to anneal out the implant damage and to diffuse the implanted nitrogen to the substrate and silicon oxide interface to cause SiN bonds to be formed at that interface. The SiN bonds are desirable because they improve the bonding strength at the interface and the nitrogen remaining in the silicon oxide layer increases the oxide bulk reliability.

Abstract translation: 用于ONO闪速存储器件的栅极结构包括在半导体衬底的顶部上的第一氧化硅层，第二层氧化硅，夹在两个氧化硅层之间的氮化硅层和位于两个氧化硅层之上的控制栅极 第二层氧化硅。 将氮注入到第一层氧化硅中，然后使用快速热工具来加热半导体结构，以退出植入物损伤并将植入的氮扩散到衬底和氧化硅界面，以在该位置形成SiN键 接口。 SiN键是期望的，因为它们改善了界面处的结合强度，并且保留在氧化硅层中的氮增加了氧化物体的可靠性。

公开(公告)号：US08598645B2

公开(公告)日：2013-12-03

申请号：US12910331

申请日：2010-10-22

Applicant: Unsoon Kim ,  Angela T. Hui ,  Yider Wu ,  Kuo-Tung Chang ,  Hiroyuki Kinoshita

Inventor： Unsoon Kim ,  Angela T. Hui ,  Yider Wu ,  Kuo-Tung Chang ,  Hiroyuki Kinoshita

IPC: H01L29/788

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11531

Abstract: A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench is filled with an oxide material. The nitride layer is stripped from the memory device, forming a mesa above the trench.

Abstract translation: 提供了一种用于形成存储器件的方法。 在衬底上形成氮化物层。 蚀刻氮化物层和衬底以形成沟槽。 在沟槽的相对侧上修整氮化物层，以加宽氮化物层内的沟槽。 沟槽填充有氧化物材料。 从存储器件剥离氮化物层，在沟槽上方形成台面。

公开(公告)号：US08325518B2

公开(公告)日：2012-12-04

申请号：US12976284

申请日：2010-12-22

Applicant: Sheng-Da Liu ,  Yider Wu

Inventor： Sheng-Da Liu ,  Yider Wu

IPC: G11C11/34

CPC classification number: H01L27/11519 ,  G11C16/0416 ,  G11C16/0483 ,  H01L27/11521

Abstract: A multi-level cell NOR flash memory device includes a plurality of gate lines, a plurality of source regions, a plurality of drain regions, a plurality of source lines, a plurality of bitlines, and a plurality of power lines. The bitlines each have a specific sheet resistance. A specific number of the bitlines are disposed between two adjacent ones of the power lines. Accordingly, the multi-level cell NOR flash memory device is of a high transconductance and uniformity and thereby features an enhanced conforming rate.

Abstract translation: 多级单元NOR闪速存储器件包括多个栅极线，多个源极区，多个漏极区，多个源极线，多个位线和多条电源线。 每个位线都具有特定的薄层电阻。 特定数量的位线布置在两条相邻的电源线之间。 因此，多电平单元NOR闪存器件具有高的跨导和均匀性，从而具有增强的一致性。

公开(公告)号：US08158519B2

公开(公告)日：2012-04-17

申请号：US12254022

申请日：2008-10-20

Applicant: Yi-Hsiu Chen ,  Yung-Chung Lee ,  Yider Wu

Inventor： Yi-Hsiu Chen ,  Yung-Chung Lee ,  Yider Wu

IPC: H01L21/84 ,  H01L21/00 ,  H01L21/8238 ,  H01L21/44

CPC classification number: H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  Y10S438/976

Abstract: In a method of manufacturing a non-volatile memory cell, a self-aligned metal silicide is used in place of a conventional tungsten metal layer to form a polysilicon gate, and the self-aligned metal silicide is used as a connection layer on the polysilicon gate. By using the self-aligned metal silicide to form the polysilicon gate, the use of masks in the etching process may be saved to thereby enable simplified manufacturing process and accordingly, reduced manufacturing cost. Meanwhile, the problem of resistance shift caused by an oxidized tungsten metal layer can be avoided.

Abstract translation: 在制造非易失性存储单元的方法中，使用自对准金属硅化物代替常规钨金属层以形成多晶硅栅极，并且自对准金属硅化物用作多晶硅上的连接层 门。 通过使用自对准的金属硅化物来形成多晶硅栅极，可以节省在蚀刻工艺中使用掩模，从而能够简化制造工艺，从而降低制造成本。 同时，可以避免由氧化的钨金属层引起的电阻偏移的问题。

公开(公告)号：US08093646B1

公开(公告)日：2012-01-10

申请号：US11432495

申请日：2006-05-12

Applicant: Angela Hui ,  Yider Wu

Inventor： Angela Hui ,  Yider Wu

IPC: H01L29/788

CPC classification number: H01L21/28273 ,  H01L29/7881

Abstract: The present invention provides a flash memory device and method for making the same having a floating gate structure with a semiconductor substrate and shallow trench isolation (STI) structure formed in the substrate. A first polysilicon layer is formed over the substrate and the STI structure. The recess formed within the first polysilicon layer is over the STI structure and extends through the first polysilicon layer to the STI structure. An oxide fill is provided within the recess and is etched back. ONO (oxide-nitride-oxide) layer conformally covers the oxide fill and the first polysilicon layer. The second polysilicon layer covers the ONO layer. The oxide fill within the recess provides a minimum spacing between the second polysilicon layer and the corner of the STI regions, thereby avoiding the creation of a weak spot and reducing the risk of gate breakdown, gate leakage, and improving device reliability.

Abstract translation: 本发明提供了一种闪存器件及其制造方法，其具有在衬底中形成的具有半导体衬底和浅沟槽隔离（STI）结构的浮动栅极结构。 在衬底和STI结构上形成第一多晶硅层。 形成在第一多晶硅层内的凹槽在STI结构之上并且延伸穿过第一多晶硅层到STI结构。 在凹槽内设置氧化物填充物并被回蚀。 ONO（氧化物 - 氧化物 - 氧化物）层保形地覆盖氧化物填充物和第一多晶硅层。 第二多晶硅层覆盖ONO层。 凹陷内的氧化物填充提供了第二多晶硅层与STI区域的拐角之间的最小间隔，从而避免了产生弱点并降低了栅极击穿，栅极泄漏和提高器件可靠性的风险。

公开(公告)号：US07842618B2

公开(公告)日：2010-11-30

申请号：US11193409

申请日：2005-08-01

Applicant: Unsoon Kim ,  Angela T. Hui ,  Yider Wu ,  Kuo-Tung Chang ,  Hiroyuki Kinoshita

Inventor： Unsoon Kim ,  Angela T. Hui ,  Yider Wu ,  Kuo-Tung Chang ,  Hiroyuki Kinoshita

IPC: H01L21/302 ,  B44C1/22

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11531

Abstract: A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench is filled with an oxide material. The nitride layer is stripped from the memory device, forming a mesa above the trench.

Abstract translation: 提供了一种用于形成存储器件的方法。 在衬底上形成氮化物层。 蚀刻氮化物层和衬底以形成沟槽。 在沟槽的相对侧上修整氮化物层，以加宽氮化物层内的沟槽。 沟槽填充有氧化物材料。 从存储器件剥离氮化物层，在沟槽上方形成台面。

公开(公告)号：US20100171161A1

公开(公告)日：2010-07-08

申请号：US12350298

申请日：2009-01-08

Applicant: Yider Wu ,  Yung-Chung Lee ,  Yi-Hsiu Chen

Inventor： Yider Wu ,  Yung-Chung Lee ,  Yi-Hsiu Chen

IPC: H01L29/788 ,  H01L29/00 ,  H01L21/336

CPC classification number: H01L27/11521 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

Abstract: In a method of manufacturing a double-implant NOR flash memory structure, a phosphorus ion implantation process is performed, so that a P-doped drain region is formed in a semiconductor substrate between two gate structures to overlap with a highly-doped drain (HDD) region and a lightly-doped drain (LDD) region. Therefore, the electric connection at a junction between the HDD region and the LDD region is enhanced and the carrier mobility in the memory is not lowered while the problems of short channel effect and punch-through of LDD region are solved.

Abstract translation: 在制造双注入NOR NOR闪存结构的方法中，执行磷离子注入工艺，使得在两个栅极结构之间的半导体衬底中形成P掺杂漏极区，以与高掺杂漏极（HDD ）区域和轻掺杂漏极（LDD）区域。 因此，解决了HDD区域和LDD区域之间的连接处的电连接，并且解决了存储器中的载流子迁移率，同时解决了LDD区域的短沟道效应和穿通问题。

公开(公告)号：US20100090256A1

公开(公告)日：2010-04-15

申请号：US12249152

申请日：2008-10-10

Applicant: Hung-Wei Chen ,  Yider Wu

Inventor： Hung-Wei Chen ,  Yider Wu

IPC: H01L29/04

CPC classification number: H01L29/045 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/7843 ,  H01L29/7881

Abstract: A semiconductor structure with stress regions includes a substrate defining a first and a second device zone; a first and a second stress region formed in each of the first and second device zones to yield stress different in level; and a barrier plug separating the two device zones from each other. Due to the stress yielded at the stress regions, increased carrier mobility and accordingly, increased reading current can be obtained, and a relatively lower reading voltage is needed to obtain initially required reading current. As a result, the probability of stress-induced leakage current (SILC) is reduced and the semiconductor memory structure may have enhanced data retention ability.

Abstract translation: 具有应力区域的半导体结构包括限定第一和第二器件区的衬底; 形成在所述第一和第二装置区域中的每一个中的第一和第二应力区域，以产生不同水平的应力; 以及将两个装置区彼此分开的阻挡塞。 由于在应力区产生的应力，载流子迁移率增加，因此可以获得增加的读取电流，并且需要相对较低的读取电压来获得最初需要的读取电流。 结果，应力诱发漏电流（SILC）的概率降低，并且半导体存储器结构可能具有增强的数据保留能力。

公开(公告)号：US20080273399A1

公开(公告)日：2008-11-06

申请号：US11762369

申请日：2007-06-13

Applicant: Chao Yang Chen ,  Yider Wu ,  Hsiao Hua Lu

Inventor： Chao Yang Chen ,  Yider Wu ,  Hsiao Hua Lu

IPC: G11C16/04

CPC classification number: G11C16/0433

Abstract: A single-poly non-volatile memory includes a storing node, a control node and a floating gate. While a programming operation is executed, a bit line is provided with a low voltage and a control line is provided with a high voltage so that a coupling voltage occurs in the floating gate. The voltage difference between the floating gate and the storing node is able to send electrons into the floating gate, but the voltage difference between the floating gate and the control node is not enough to expel electrons from the floating gate. While an erasing operation is executed, a bit line is provided with a high voltage and a control line is provided with a low voltage so that a coupling voltage occurs on the floating gate. The voltage difference between the floating gate and the storing node is able to expel electrons from the floating gate, but the voltage difference between the floating gate and the control node is not enough to send electrons into the floating gate.

Abstract translation: 单聚多边形非易失性存储器包括存储节点，控制节点和浮动门。 当执行编程操作时，位线被提供有低电压，并且控制线被提供有高电压，使得在浮动栅极中发生耦合电压。 浮动栅极和存储节点之间的电压差能够将电子发送到浮动栅极，但是浮动栅极和控制节点之间的电压差不足以从浮动栅极排出电子。 当执行擦除操作时，位线被提供有高电压，并且控制线设置有低电压，使得在浮动栅极上发生耦合电压。 浮栅和存储节点之间的电压差能够从浮置栅极排出电子，但是浮栅和控制节点之间的电压差不足以将电子发送到浮置栅极。