公开(公告)号：US06466482B2

公开(公告)日：2002-10-15

申请号：US09801769

申请日：2001-03-09

申请人： Shoji Shukuri ,  Kazumasa Yanagisawa

发明人： Shoji Shukuri ,  Kazumasa Yanagisawa

IPC分类号： G11C700

CPC分类号： G11C16/26 ,  G11C16/0441 ,  G11C2216/10

摘要： A semiconductor integrated circuit includes non-volatile memory elements (PM1, PM2), each of which has a first source electrode, a first drain electrode, a floating gate electrode and a control gate electrode and is capable of having different threshold voltages, and read transistor elements (DM1, DM2), each of which has a second source electrode and a second drain electrode and is capable of having different mutual conductances according to the threshold voltage of the non-volatile memory element. The read transistor element has a switching state according to the electron injection state or the electron emission state, in other words, the writing state or the erasing state of the floating gate electrode. In a read operation, it is not necessary to cause a channel current to flow according to the threshold voltage of the non-volatile memory element.

摘要翻译： 半导体集成电路包括非易失性存储元件（PM1，PM2），其中每一个具有第一源电极，第一漏电极，浮栅电极和控制栅电极，并且能够具有不同的阈值电压，并读取 晶体管元件（DM1，DM2），每个晶体管元件具有第二源极和第二漏极，并且能够根据非易失性存储元件的阈值电压具有不同的互导。 读取晶体管元件具有根据电子注入状态或电子发射状态的切换状态，换句话说，浮置栅电极的写入状态或擦除状态。 在读取操作中，不需要根据非易失性存储元件的阈值电压使通道电流流动。

公开(公告)号：US06301184B1

公开(公告)日：2001-10-09

申请号：US09480695

申请日：2000-01-11

申请人： Toshio Sasaki ,  Yoshihiko Yasu ,  Kazumasa Yanagisawa ,  Yuji Tanaka ,  Toshiaki Takahira ,  Yasuto Igarashi ,  Mariko Ohtsuka ,  Yasunobu Aoki

发明人： Toshio Sasaki ,  Yoshihiko Yasu ,  Kazumasa Yanagisawa ,  Yuji Tanaka ,  Toshiaki Takahira ,  Yasuto Igarashi ,  Mariko Ohtsuka ,  Yasunobu Aoki

IPC分类号： G11C800

CPC分类号： G11C11/4074 ,  G11C7/1045

摘要： A DRAM module is applied to the system LSI which is provided with a standby mode for suppressing the whole operation thereof and an operation standby mode which permits at least the DRAM module to operate but suppresses the operation of other circuits. The above-mentioned modes as well as a substrate bias control technology are applied to the CMOS system LSI that operates on a low voltage. The system LSI is controlled to hold or not to hold data, enabling a memory of a large capacity to be mounted and consuming a sufficiently decreased amount of electric power.

摘要翻译： 将DRAM模块应用于具有用于抑制其整体操作的待机模式的系统LSI和至少允许DRAM模块操作但抑制其它电路的操作的操作待机模式。 将上述模式以及衬底偏置控制技术应用于在低电压下工作的CMOS系统LSI。 控制系统LSI以保持或不保存数据，使得能够安装大容量的存储器并消耗足够的电力量。

公开(公告)号：US06249524B1

公开(公告)日：2001-06-19

申请号：US09044171

申请日：1998-03-19

申请人： Norihiko Moriwaki ,  Kenichi Sakamoto ,  Akihiko Takase ,  Akio Makimoto ,  Kazumasa Yanagisawa

发明人： Norihiko Moriwaki ,  Kenichi Sakamoto ,  Akihiko Takase ,  Akio Makimoto ,  Kazumasa Yanagisawa

IPC分类号： H04J324

CPC分类号： H04L49/108 ,  H04Q11/0478

摘要： Provided is a high-throughput large-capacity ATM switch in which variation in memory access time and data output delay time generated in the case where a DRAM is used as a cell buffer of the ATM switch is absorbed. To realize this, the ATM switch comprises a first memory using a DRAM for storing cells, a second memory using an SRAM for switching and temporarily storing the cells before transferring the cells to the first memory, and a controller for generating write/read address and timing signals for the first and second memories. The controller generates read address and timing signals for the second memory and write address and timing signals for the first memory taking variation in access time or delay time based on access address of the first memory into account, so that the cells are output on destination output lines after the cells are switched and stored in the second memory and then stored in the first memory.

摘要翻译： 提供了一种高吞吐量大容量ATM交换机，其中在将DRAM用作ATM交换机的小区缓冲器的情况下产生的存储器访问时间和数据输出延迟时间的变化被吸收。 为了实现这一点，ATM交换机包括使用用于存储单元的DRAM的第一存储器，使用SRAM的第二存储器，用于在将单元传送到第一存储器之前切换和临时存储单元;以及控制器，用于产生写/ 用于第一和第二存储器的定时信号。 控制器产生用于第二存储器的读取地址和定时信号，并且基于第一存储器的存取地址来考虑第一存储器的存取时间或延迟时间的变化的写入地址和定时信号，从而在目的地输出 将单元切换并存储在第二存储器中，然后存储在第一存储器中。

公开(公告)号：US5818792A

公开(公告)日：1998-10-06

申请号：US804683

申请日：1997-02-25

申请人： Toshio Sasaki ,  Kazumasa Yanagisawa ,  Toshio Sugano ,  Kiyoshi Inoue ,  Seiichiro Tsukui ,  Masakazu Aoki ,  Shigeru Suzuki ,  Masashi Horiguchi

发明人： Toshio Sasaki ,  Kazumasa Yanagisawa ,  Toshio Sugano ,  Kiyoshi Inoue ,  Seiichiro Tsukui ,  Masakazu Aoki ,  Shigeru Suzuki ,  Masashi Horiguchi

IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/108 ,  G01C13/00

CPC分类号： G11C29/80 ,  G11C29/74 ,  G11C29/808 ,  G11C29/832

摘要： Input/output terminals of a first semiconductor memory device in which failures or defects exist in units of memory mats and input/output terminals of a second semiconductor memory device having redundant memory mats are connected to one another on a mounted substrate to thereby relieve the failures in the memory mat units. A power source is substantially cut off from supplying to a faulty memory mat.

摘要翻译： 第一半导体存储器件的输入/输出端子，其中存在以存储器单元为单位的故障或缺陷，并且具有冗余存储器垫的第二半导体存储器件的输入/输出端子在安装的基板上彼此连接，从而减轻故障 在记忆垫单位。 电源基本上被切断供给故障存储器垫。

公开(公告)号：US5274594A

公开(公告)日：1993-12-28

申请号：US840819

申请日：1992-02-25

申请人： Kazumasa Yanagisawa ,  Atsushi Hiraishi ,  Hideyuki Aoki ,  Satoshi Oguchi ,  Sadayuki Ohkuma

发明人： Kazumasa Yanagisawa ,  Atsushi Hiraishi ,  Hideyuki Aoki ,  Satoshi Oguchi ,  Sadayuki Ohkuma

IPC分类号： G11C11/413 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L27/10 ,  G11C7/00

CPC分类号： G11C29/80 ,  G11C29/832 ,  G11C29/84

摘要： A static RAM comprises: column select circuits for connecting a plurality of pairs of corresponding complementary data lines at a unit of each pair with common complementary data lines; and redundant circuits each composed of the complementary data line pair and the column select circuit corresponding to the unit. Load MOSFETs of the complementary data lines are arranged close to the column select circuits to inhibit the column selecting operations by a decoder circuit and turn off the load MOSFETs when fuse means is cut. An access to a defective address is detected by a redundant decoder stored with the defective address, when the fuse means is selectively cut, to select the column select circuits of the redundant circuit.

摘要翻译： 静态RAM包括：列选择电路，用于以每对的单位将多对相应的互补数据线对与公共补充数据线连接; 以及各自由互补数据线对和与该单元对应的列选择电路组成的冗余电路。 互补数据线的负载MOSFET布置成靠近列选择电路，以禁止解码器电路的列选择操作，并且当熔断装置被切断时关断负载MOSFET。 当选择性地切断熔丝装置时，通过存储有缺陷地址的冗余解码器来检测缺陷地址，以选择冗余电路的列选择电路。

公开(公告)号：US5187685A

公开(公告)日：1993-02-16

申请号：US749851

申请日：1991-08-26

申请人： Katsuyuki Sato ,  Hiroshi Kawamoto ,  Kazumasa Yanagisawa

发明人： Katsuyuki Sato ,  Hiroshi Kawamoto ,  Kazumasa Yanagisawa

IPC分类号： G11C11/4074 ,  G11C29/50

CPC分类号： G11C29/50016 ,  G11C11/4074 ,  G11C29/50 ,  G11C11/401 ,  G11C2029/5004

摘要： A voltage generating circuit having a voltage dividing circuit of complementary MISFETs is provided in an arrangement wherein a controlled output voltage, such as a bias voltage applied to plate electrodes of storage cells in a RAM, is obtained. The voltage dividing circuit has a series arrangement, between the power source voltage and a predetermined voltage, such as ground potential, of a first resistance, a first diode-connected MISFET, a second resistance and a second diode connected MISFET. Also, the voltage generator circuit has a first output MISFET of a first channel conductivity type having its gate coupled to the common connection of the first diode-connected MISFET and first resistance as well as a second output MISFET of the second conductivity type in series therewith which has a gate coupled to the common connection of the second diode-connected MISFET and second resistance. The first and second output MISFETs have their drains respectively coupled to receive the power source voltage and predetermined voltage and the source of the first output MISFET is coupled with the source of the second output MISFET wherein an output voltage of about 1/2 the potential of the power source voltage is obtained.

摘要翻译： 具有互补MISFET的分压电路的电压产生电路被提供在其中获得诸如施加到RAM中的存储单元的板电极的偏置电压的受控输出电压的布置中。 分压电路具有电源电压和第一电阻，第一二极管连接的MISFET，第二电阻和第二二极管连接的MISFET的预定电压（例如接地电位）之间的串联布置。 此外，电压发生器电路具有第一沟道导电类型的第一输出MISFET，其栅极连接到第一二极管连接的MISFET和第一电阻的公共连接以及与其串联的第二导电类型的第二输出MISFET。 其具有耦合到第二二极管连接的MISFET和第二电阻的公共连接的栅极。 第一和第二输出MISFET的漏极分别耦合以接收电源电压和预定电压，并且第一输出MISFET的源极与第二输出MISFET的源耦合，其中输出电压约为 获得电源电压。

公开(公告)号：US4961166A

公开(公告)日：1990-10-02

申请号：US729859

申请日：1985-05-02

申请人： Katsuyuki Sato ,  Kazumasa Yanagisawa ,  Kunio Ono

发明人： Katsuyuki Sato ,  Kazumasa Yanagisawa ,  Kunio Ono

IPC分类号： G11C11/4096 ,  G11C11/4099

CPC分类号： G11C11/4096 ,  G11C11/4099

摘要： A dynamic RAM, in which the difference between a data signal level from one of a pair of complementary data lines coupled to a memory cell and a reference potential level of the other of the complementary data lines is differentially amplified by a sense amplifier. The data line taking the reference potential level is coupled to the other data line through a switch element so that its data line capacitance is increased. As a result, the reference potential level is held at a relatively stable level irrespective of a leakage current such as that caused by .alpha. particles. This construction makes it possible to use a full-size dummy cell because the capacitance of the data lines which takes the reference potential level is increased. The reference potential level achieved by the use of the full-size dummy cell is made relatively accurate because of the relative accuracy between the capacitances of the memory cells and the capacitance of the full-size dummy cell.

摘要翻译： 动态RAM，其中来自耦合到存储单元的一对互补数据线中的一个的数据信号电平与另一个互补数据线的参考电位电平之间的差异由读出放大器差分放大。 采用参考电位电平的数据线通过开关元件耦合到另一条数据线，使其数据线电容增加。 结果，不管诸如由α粒子引起的漏电流如何，基准电位电平保持在相对稳定的水平。 这种结构使得可以使用全尺寸虚拟单元，因为增加了参考电位电平的数据线的电容。 由于存储单元的电容与全尺寸虚拟单元的电容之间的相对精度相对较高，因此通过使用全尺寸虚拟单元实现的参考电位水平相对精确。

公开(公告)号：US4736344A

公开(公告)日：1988-04-05

申请号：US843612

申请日：1986-03-25

申请人： Kazumasa Yanagisawa

发明人： Kazumasa Yanagisawa

IPC分类号： G11C11/401 ,  G11C11/403 ,  G11C11/406 ,  G11C7/00

CPC分类号： G11C11/406

摘要： A refresh arrangement is provided for a dynamic RAM wherein each time a refresh address counter performs a predetermined plurality of steps of increment operations, an address switching circuit is switched to specified refresh addresses held in an address storage circuit to provide addresses of memory cells having inferior data retention times. In this way the memory cells with inferior data retention times can be refreshed much more frequently than memory cells with normal data retention times.

摘要翻译： 为动态RAM提供刷新布置，其中每次刷新地址计数器执行预定的多个递增操作步骤时，将地址切换电路切换到保存在地址存储电路中的指定的刷新地址，以提供具有较差的存储单元的地址 数据保留时间。 以这种方式，具有较差数据保留时间的存储器单元可以比具有正常数据保留时间的存储器单元更频繁地刷新。

公开(公告)号：US08576643B2

公开(公告)日：2013-11-05

申请号：US13368461

申请日：2012-02-08

申请人： Yutaka Shinagawa ,  Takeshi Kataoka ,  Eiichi Ishikawa ,  Toshihiro Tanaka ,  Kazumasa Yanagisawa ,  Kazufumi Suzukawa

发明人： Yutaka Shinagawa ,  Takeshi Kataoka ,  Eiichi Ishikawa ,  Toshihiro Tanaka ,  Kazumasa Yanagisawa ,  Kazufumi Suzukawa

IPC分类号： G11C7/00

CPC分类号： G11C16/349 ,  G11C16/06 ,  G11C16/3495

摘要： A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has a maximum variation width of a threshold voltage for memorizing an information set larger than that of the second nonvolatile memory area. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information, and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information.

摘要翻译： 半导体集成电路具有设置在中央处理单元的地址空间中的中央处理单元和可重写的非易失性存储区域。 非易失性存储区域具有第一非易失性存储区域和第二非易失性存储器区域，其根据阈值电压的差异来存储信息。 第一非易失性存储区具有用于存储大于第二非易失性存储区的信息集的阈值电压的最大变化宽度。 可以优先考虑第一非易失性存储器区域以加快存储器信息的读取速度，并且可以对第二非易失性存储器区域进行优先排列以保证存储器信息的重写操作的次数。

公开(公告)号：US07977238B2

公开(公告)日：2011-07-12

申请号：US12764411

申请日：2010-04-21

申请人： Takako Funakoshi ,  Eiichi Murakami ,  Kazumasa Yanagisawa ,  Kan Takeuchi ,  Hideo Aoki ,  Hizuru Yamaguchi ,  Takayuki Oshima ,  Kazuyuki Tsunokuni ,  Kousuke Okuyama

发明人： Takako Funakoshi ,  Eiichi Murakami ,  Kazumasa Yanagisawa ,  Kan Takeuchi ,  Hideo Aoki ,  Hizuru Yamaguchi ,  Takayuki Oshima ,  Kazuyuki Tsunokuni ,  Kousuke Okuyama

IPC分类号： H01L21/4763

CPC分类号： H01L23/53238 ,  H01L21/823871 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： A manufacturing technique is disclosed for producing a semiconductor integrated circuit device having plural layers of buried wirings, and such that there is prevented the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 μm and is smaller than about 1.44 μm, and the width of a second Cu wiring and the diameter of a plug are about 0.18 μm, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.

摘要翻译： 公开了一种用于制造具有多层埋置布线的半导体集成电路器件的制造技术，并且防止了在其底部连接到埋地布线的插头与嵌入布线之间的界面处的应力迁移引起的不连续性的发生，以及 埋地线。 例如，在第一Cu布线的宽度不小于约0.9μm且小于约1.44μm的情况下，并且第二Cu布线的宽度和塞子的直径为约0.18μm的情况下，存在 布置两个或更多个将第一布线和第二铜布线彼此电连接的插头。