公开(公告)号：US5274594A

公开(公告)日：1993-12-28

申请号：US840819

申请日：1992-02-25

申请人： Kazumasa Yanagisawa ,  Atsushi Hiraishi ,  Hideyuki Aoki ,  Satoshi Oguchi ,  Sadayuki Ohkuma

发明人： Kazumasa Yanagisawa ,  Atsushi Hiraishi ,  Hideyuki Aoki ,  Satoshi Oguchi ,  Sadayuki Ohkuma

IPC分类号： G11C11/413 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L27/10 ,  G11C7/00

CPC分类号： G11C29/80 ,  G11C29/832 ,  G11C29/84

摘要： A static RAM comprises: column select circuits for connecting a plurality of pairs of corresponding complementary data lines at a unit of each pair with common complementary data lines; and redundant circuits each composed of the complementary data line pair and the column select circuit corresponding to the unit. Load MOSFETs of the complementary data lines are arranged close to the column select circuits to inhibit the column selecting operations by a decoder circuit and turn off the load MOSFETs when fuse means is cut. An access to a defective address is detected by a redundant decoder stored with the defective address, when the fuse means is selectively cut, to select the column select circuits of the redundant circuit.

摘要翻译： 静态RAM包括：列选择电路，用于以每对的单位将多对相应的互补数据线对与公共补充数据线连接; 以及各自由互补数据线对和与该单元对应的列选择电路组成的冗余电路。 互补数据线的负载MOSFET布置成靠近列选择电路，以禁止解码器电路的列选择操作，并且当熔断装置被切断时关断负载MOSFET。 当选择性地切断熔丝装置时，通过存储有缺陷地址的冗余解码器来检测缺陷地址，以选择冗余电路的列选择电路。

公开(公告)号：US08922029B2

公开(公告)日：2014-12-30

申请号：US13363396

申请日：2012-02-01

申请人： Atsushi Hiraishi ,  Toshio Sugano ,  Masahiro Yamaguchi ,  Yoji Nishio ,  Tsutomu Hara ,  Koichiro Aoki

发明人： Atsushi Hiraishi ,  Toshio Sugano ,  Masahiro Yamaguchi ,  Yoji Nishio ,  Tsutomu Hara ,  Koichiro Aoki

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  G11C5/06 ,  G11C5/04 ,  G11C8/14 ,  H05K1/18

CPC分类号： G11C5/063 ,  G11C5/04 ,  G11C8/14 ,  H05K1/181 ,  H05K2201/09254 ,  H05K2201/09263 ,  H05K2201/10159 ,  Y02P70/611

摘要： An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.

摘要翻译： 具有短截线结构的地址信号线连接在至少三个存储器元件和数据传输元件之间，并传送存储器元件的地址信号。 数据传送元件的地址端子的阻抗低于地址信号线的特性阻抗。 从数据传送元件到分支线从数据传送元件到最短距离分支的第一分支点S1的布线长度TL0被配置成等于或大于从第一分支点S1到布线长度TL1 第二分支点S2，其中第二支线被分支。 从第二分支点S2到分支第三分支线的第三分支点S3的布线长度TL3被配置为变得大于布线长度TL0和TL1。

公开(公告)号：US20100309706A1

公开(公告)日：2010-12-09

申请号：US12801326

申请日：2010-06-03

申请人： Shunichi Saito ,  Toshio Sugano ,  Atsushi Hiraishi ,  Fumiyuki Osanai ,  Masayuki Nakamura ,  Hiroki Fujisawa

发明人： Shunichi Saito ,  Toshio Sugano ,  Atsushi Hiraishi ,  Fumiyuki Osanai ,  Masayuki Nakamura ,  Hiroki Fujisawa

IPC分类号： G11C5/02 ,  G11C7/00

CPC分类号： G11C7/00 ,  G11C5/02 ,  G11C5/04 ,  G11C5/063 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/109 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/00014

摘要： A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate.

摘要翻译： 存储器模块包括多个存储器芯片，多个数据寄存器缓冲器以及安装在模块PCB上的命令/地址/控制寄存器缓冲器。 数据寄存器缓冲器与存储器芯片执行数据传输。 命令/地址/控制寄存器缓冲器执行命令/地址/控制信号的缓冲并产生控制信号。 缓冲的命令/地址/控制信号被提供给存储器芯片，并且控制信号被提供给数据寄存器缓冲器。 根据本发明，由于数据寄存器缓冲器和存储器芯片之间的线路长度被缩短，可以实现相当高的数据传输速率。

公开(公告)号：US07667317B2

公开(公告)日：2010-02-23

申请号：US11802888

申请日：2007-05-25

申请人： Fumiyuki Osanai ,  Atsushi Hiraishi ,  Toshio Sugano ,  Tsuyoshi Tomoyama ,  Satoshi Isa ,  Masahiro Yamaguchi ,  Masanori Shibamoto

发明人： Fumiyuki Osanai ,  Atsushi Hiraishi ,  Toshio Sugano ,  Tsuyoshi Tomoyama ,  Satoshi Isa ,  Masahiro Yamaguchi ,  Masanori Shibamoto

IPC分类号： H01L23/055

CPC分类号： H01L23/50 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor package comprises a substrate, which has two surfaces and comprises first and second electrical paths. On one of the surfaces, a semiconductor chip is mounted. The semiconductor chip comprises a plurality of pads, which include a first pad to be supplied with a power supply and a second pad to be grounded. On the other surface, at least one bypass capacitor is mounted. The bypass capacitor comprises first and second terminals, which are connected to the first and the second pads through the first and the second electrical paths, respectively.

摘要翻译： 半导体封装包括具有两个表面并且包括第一和第二电路径的衬底。 在其中一个表面上安装了半导体芯片。 半导体芯片包括多个焊盘，其包括要供应电源的第一焊盘和要接地的第二焊盘。 在另一个表面上，安装至少一个旁路电容器。 旁路电容器包括分别通过第一和第二电路连接到第一和第二焊盘的第一和第二端子。

公开(公告)号：US20080164058A1

公开(公告)日：2008-07-10

申请号：US12004020

申请日：2007-12-20

申请人： Shunichi Saito ,  Toshio Sugano ,  Atsushi Hiraishi

发明人： Shunichi Saito ,  Toshio Sugano ,  Atsushi Hiraishi

IPC分类号： H05K1/11

CPC分类号： H05K1/112 ,  H05K1/0237 ,  H05K1/0298 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09518 ,  H05K2201/09627 ,  H05K2201/10159 ,  H05K2201/10734

摘要： A multi-layer printed circuit board for mounting memories, includes: laminated wiring layers on which wiring are arranged; and a plurality of interlayer connection components which electrically connect at least two of the wiring layers. At least one of the plurality of interlayer connection components is a blind via-hole.

摘要翻译： 一种用于安装存储器的多层印刷电路板，包括：布置布线的层叠布线层; 以及电连接至少两个所述布线层的多个层间连接部件。 多个层间连接部件中的至少一个是盲通孔。

公开(公告)号：US20070213428A1

公开(公告)日：2007-09-13

申请号：US11714855

申请日：2007-03-07

申请人： Atsushi Hiraishi ,  Takehiro Tsutsumi

发明人： Atsushi Hiraishi ,  Takehiro Tsutsumi

IPC分类号： C09D11/00 ,  B60C1/00

CPC分类号： C09D11/322 ,  C09D11/30

摘要： A water dispersion for inkjet printing which includes water-insoluble polymer particles. The water-insoluble polymer particles contain silica particles and a pigment other than the silica particles. A water-based ink containing the water dispersion is excellent in the storage stability and effectively reduces the bronze phenomenon of printed images.

摘要翻译： 用于喷墨印刷的水分散体，其包括水不溶性聚合物颗粒。 水不溶性聚合物粒子含有二氧化硅粒子和二氧化硅粒子以外的颜料。 含有水分散体的水性油墨的储存稳定性优异，有效地减少了印刷图像的青铜现象。

公开(公告)号：US5834851A

公开(公告)日：1998-11-10

申请号：US460641

申请日：1995-06-02

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

IPC分类号： H01L27/11

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

摘要： Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially. The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.The source line is formed of a conductive layer identical to that of the word line. The individual data lines of the complementary data line are formed of an identical conductive layer which is different from that of the word line and the source line. The identical conductive layer between the word line and source line and the complementary data line is formed with two word lines: a main word line extended in the first direction identical to that of the word line and source line and used by adopting the divided word line system: and a sub-word line used by adopting the double word line system.

摘要翻译： 这里公开了一种半导体集成电路器件，其包括具有其存储单元的SRAM，SRAM由通过字线控制的转移MISFET和驱动MISFET构成。 驱动MISFET的栅电极和存储单元的转移MISFET的栅电极和字线分别由不同的导电层形成。 驱动MISFET和转移MISFET分别布置成在栅极长度方向上彼此交叉。 字线在驱动MISFET的栅电极的栅极长度方向上延伸，并且部分地与驱动MISFET的栅电极交叉。 存储器单元的两个转移MISFET的各自的栅极电极与彼此间隔开并沿相同方向延伸的两个相应字线连接。 由两个字线限定的区域配置有两个驱动MISFET和源极线。 源极线由与字线的导电层相同的导电层形成。 互补数据线的各个数据线由与字线和源极线不同的导电层形成。 字线和源极线与互补数据线之间的相同的导电层由两条字线形成：主字线在第一方向上延伸，与字线和源极线相同，并通过采用分割字线 系统：采用双字线系统使用的子字线。

公开(公告)号：US5680066A

公开(公告)日：1997-10-21

申请号：US182699

申请日：1994-01-13

申请人： Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yuji Yokoyama ,  Nozomu Matsuzaki ,  Tatsumi Yamauchi ,  Yutaka Kobayashi ,  Nobuyuki Gotou ,  Akira Ide ,  Masahiro Yamamura ,  Hideaki Uchida

发明人： Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yuji Yokoyama ,  Nozomu Matsuzaki ,  Tatsumi Yamauchi ,  Yutaka Kobayashi ,  Nobuyuki Gotou ,  Akira Ide ,  Masahiro Yamamura ,  Hideaki Uchida

IPC分类号： G11C7/10 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  H03K5/1534 ,  H03K19/0175 ,  H03K5/153 ,  G01R29/02 ,  H03K3/033

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  H03K19/017518 ,  H03K5/1534

摘要： A semiconductor device which includes at least one of (1) an input buffer circuit formed of an input level converter and a non-inverting buffer circuit and an inverting buffer circuit each including BiCMOS circuitry which effects high-speed operation; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitude signals and, in response thereto, generates an ATD signal of a voltage amplitude; and (5) an output buffer circuit, in which the decoder, sense amplifier and output buffer of the device such as for a memory are controlled in accordance with signals from a clock generator, which is responsive to the ATD signal.

摘要翻译： 一种半导体器件，其包括以下中的至少一个：（1）由输入电平转换器和非反相缓冲电路构成的输入缓冲电路和各自包括实现高速操作的BiCMOS电路的反相缓冲电路; （2）由多个逻辑门形成的解码器电路，每个逻辑门由MOS和双极电路的组合组成; （3）包括多端子晶体管的读出放大器电路; （4）信号或地址转换检测器电路，其包括各自接收例如电压幅度的地址信号并且响应于地址信号的电平的变化而输出当前振幅信号的输入电路，以及连接的检测器电路 具有共源共栅放大器，其布置成使得其在其输入处接收电流幅度信号，并且其中共源共栅放大器输入保持在基本上恒定的电压，其中检测电路检测到一个或多个当前幅度信号的转变 并且响应于此产生电压幅度的ATD信号; 以及（5）输出缓冲器电路，其中根据来自响应于ATD信号的时钟发生器的信号来控制诸如存储器的装置的解码器，读出放大器和输出缓冲器。

公开(公告)号：US5387827A

公开(公告)日：1995-02-07

申请号：US643372

申请日：1991-01-22

申请人： Yuji Yokoyama ,  Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Nobuyuki Gotou ,  Akira Ide

发明人： Yuji Yokoyama ,  Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Nobuyuki Gotou ,  Akira Ide

IPC分类号： G11C7/10 ,  G11C8/10 ,  H03K19/0948 ,  H03K19/23

CPC分类号： H03K19/0948 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/10

摘要： A semiconductor integrated logic circuit is provided which includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals, wherein each of the logic gates is coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. This arrangement is particularly effective for decoders in semiconductor memory circuits which use a common NMOS to receive one input for a plurality of logic decoder gates. An improved read/write arrangement is also provided for semiconductor memory circuits which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.

摘要翻译： 提供了一种半导体集成逻辑电路，其包括多个逻辑门，每个逻辑门具有用于分别接收第一输入信号的第一输入端，其中每个逻辑门耦合到公共节点。 在一个实施例中，第一和第二开关元件也耦合到公共节点。 第一和第二开关元件都耦合到第二输入端子，用于接收多个逻辑门公共的第二输入信号，并且它们都响应于第二输入信号互相互补。 这种布置对于使用公共NMOS来接收多个逻辑解码器门的一个输入的半导体存储器电路中的解码器特别有效。 还提供了一种用于半导体存储器电路的改进的读/写布置，其包括在写入操作期间防止公共读取线连接到数据线的电路。 这通过在写入期间去除公共读取线的负载来增强写入速度。

公开(公告)号：US09368185B2

公开(公告)日：2016-06-14

申请号：US14508744

申请日：2014-10-07

申请人： Shunichi Saito ,  Toshio Sugano ,  Atsushi Hiraishi

发明人： Shunichi Saito ,  Toshio Sugano ,  Atsushi Hiraishi

IPC分类号： G11C16/26 ,  G11C11/406

CPC分类号： G11C11/40615 ,  G11C11/40603 ,  G11C16/26

摘要： A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data refresh operation on the memory cells, the access circuit to operate in a selected one of a first mode that is ready to perform and a second mode that is not ready to perform, and a judgment circuit configured to respond to first command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to exit from the second mode and then to perform the refresh operation.

摘要翻译： 半导体器件包括多个存储器单元，存取电路，被配置为对存储器单元执行数据读取操作，数据写入操作和数据刷新操作，所述存取电路以选择的第一模式操作 准备执行的第二模式和未准备好执行的第二模式;以及判断电路，被配置为响应于第一命令信息，以使得当访问电路处于第一模式时，访问电路执行数据刷新操作，以及 当访问电路处于第二模式时，访问电路从第二模式退出，然后执行刷新操作。