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    Semiconductor memory device
    3.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US4942556A

    公开(公告)日：1990-07-17

    申请号：US377181

    申请日：1989-07-10

    申请人： Toshio Sasaki ,  Masakazu Aoki ,  Masashi Horiguchi ,  Yoshinobu Nakagome ,  Shinichi Ikenaga ,  Toshiaki Masuhara

    发明人： Toshio Sasaki ,  Masakazu Aoki ,  Masashi Horiguchi ,  Yoshinobu Nakagome ,  Shinichi Ikenaga ,  Toshiaki Masuhara

    IPC分类号： G11C15/04 ,  G11C29/00 ,  G11C29/44

    CPC分类号： G11C29/76 ,  G11C15/04 ,  G11C15/046 ,  G11C29/44

    摘要： In a defect relieving technology which replaces defective memory cells of a semiconductor memory device by spare memory cells, use is made of an associative memory. Address information of a defective memory cell is stored as a reference data of the associative memory, and new address information of a spare memory cell is written down as output data of the associative memory. A variety of improvements are made to the associative memory. For instance, a plurality of coincidence detection signal lines of the associative memory are divided into at least two groups, and one group among them is selected by switching means. Reference data of the associative memory comprises three values consisting of binary information of "0" and "1", and don't care value "X". The associative memory further includes a plurality of electrically programable non-volatile semiconductor memory elements.

    摘要翻译： 在通过备用存储器单元代替半导体存储器件的缺陷存储单元的缺陷解除技术中，使用关联存储器。 存储有缺陷的存储单元的地址信息被存储为关联存储器的参考数据，并且备用存储单元的新地址信息被写入作为关联存储器的输出数据。 对联想记忆进行了各种改进。 例如，关联存储器的多个符合检测信号线被划分为至少两组，其中一组由切换装置选择。 关联存储器的参考数据包括由“0”和“1”的二进制信息组成的三个值，并且不关心值“X”。 关联存储器还包括多个可电可编程的非易失性半导体存储器元件。

    Method for manufacturing memory device provided with a defect recovery mechanism featuring a redundancy circuit
    4.
    发明授权
    Method for manufacturing memory device provided with a defect recovery mechanism featuring a redundancy circuit 失效
    一种具有冗余电路的缺陷恢复机构的存储装置的制造方法

    公开(公告)号：US07106643B2

    公开(公告)日：2006-09-12

    申请号：US11139513

    申请日：2005-05-31

    申请人： Masashi Horiguchi ,  Jun Etoh ,  Masakazu Aoki ,  Kiyoo Itoh

    发明人： Masashi Horiguchi ,  Jun Etoh ,  Masakazu Aoki ,  Kiyoo Itoh

    IPC分类号： G11C29/04 ,  G11C29/18 ,  G11C29/24 ,  G11C8/12

    CPC分类号： G11C29/80 ,  G11C29/785 ,  G11C29/808

    摘要： Method for manufacturing a memory device, the memory being a memory array with a spare bit line and being provided with a defect recovery scheme featuring a redundancy circuit. The redundancy circuit includes one or more comparing circuits having programmable elements which function as a memory for storing therein a defective address existing in the memory array. The programmable elements of the redundancy circuit can be programmed in accordance with any of a number of different types of defect modes. Each comparing circuit of the redundancy circuit compares information (data) inputted therein, for example, the column and row addresses which may be under the control of an address multiplex system, with that programmed in the programmable elements of the comparing circuit. On the basis of this comparison, an appropriate defect recovery is effected.

    摘要翻译： 用于制造存储器件的方法，所述存储器是具有备用位线的存储器阵列，并且提供具有冗余电路的缺陷恢复方案。 冗余电路包括具有可编程元件的一个或多个比较电路，其作为用于在其中存储存在于存储器阵列中的缺陷地址的存储器。 冗余电路的可编程元件可以根据多种不同类型的缺陷模式中的任何一种进行编程。 冗余电路的每个比较电路将在其中输入的信息（数据），例如可能在地址多路复用系统的控制下的列和行地址与在比较电路的可编程元件中编程的信息（数据）进行比较。 在此比较的基础上，进行适当的缺陷恢复。

    Semiconductor device having redundancy circuit
    6.
    发明授权
    Semiconductor device having redundancy circuit 失效
    具有冗余电路的半导体器件

    公开(公告)号：US06909647B2

    公开(公告)日：2005-06-21

    申请号：US10813240

    申请日：2004-03-31

    申请人： Masashi Horiguchi ,  Jun Etoh ,  Masakazu Aoki ,  Kiyoo Itoh

    发明人： Masashi Horiguchi ,  Jun Etoh ,  Masakazu Aoki ,  Kiyoo Itoh

    IPC分类号： G11C5/00 ,  G11C7/00 ,  G11C8/00 ,  G11C29/00

    CPC分类号： G11C29/80 ,  G11C29/785 ,  G11C29/808

    摘要： A semiconductor memory is provided with a defect recovery scheme featuring a redundancy circuit. The memory array in the memory has a plurality of word lines, a plurality of bit lines, a spare bit line, and a plurality of memory cells. The redundancy circuit includes one or more comparing circuits having programmable elements which function as a memory for storing therein a defective address existing in the memory array. The programmable elements of the redundancy circuit can be programmed in accordance with any of a number of different types of defect modes. Each comparing circuit of the redundancy circuit compares information (data) inputted therein, for example, the column and row addresses which may be under the control of an address multiplex system, with that programmed in the programmable elements of the comparing circuit. On the basis of this comparison, an appropriate defect recovery is effected.

    摘要翻译： 半导体存储器具有冗余电路的缺陷恢复方案。 存储器中的存储器阵列具有多个字线，多个位线，备用位线和多个存储器单元。 冗余电路包括具有可编程元件的一个或多个比较电路，其作为用于在其中存储存在于存储器阵列中的缺陷地址的存储器。 冗余电路的可编程元件可以根据多种不同类型的缺陷模式中的任何一种进行编程。 冗余电路的每个比较电路将在其中输入的信息（数据），例如可能在地址多路复用系统的控制下的列和行地址与在比较电路的可编程元件中编程的信息（数据）进行比较。 在此比较的基础上，进行适当的缺陷恢复。

    Semiconductor device having redundancy circuit
    7.
    发明授权
    Semiconductor device having redundancy circuit 失效
    具有冗余电路的半导体器件

    公开(公告)号：US06577544B2

    公开(公告)日：2003-06-10

    申请号：US09992001

    申请日：2001-11-26

    申请人： Masashi Horiguchi ,  Jun Etoh ,  Masakazu Aoki ,  Kiyoo Itoh

    发明人： Masashi Horiguchi ,  Jun Etoh ,  Masakazu Aoki ,  Kiyoo Itoh

    IPC分类号： G11C700

    CPC分类号： G11C29/80 ,  G11C29/785 ,  G11C29/808

    摘要： A semiconductor memory is provided with a defect recovery scheme featuring a redundancy circuit. The memory array in the memory has a plurality of word lines, a plurality of bit lines, a spare bit line, and a plurality of memory cells. The redundancy circuit includes one or more comparing circuits having programmable elements which function as a memory for storing therein a defective address existing in the memory array. The programmable elements of the redundancy circuit can be programmed in accordance with any of a number of different types of defect modes. Each comparing circuit of the redundancy circuit compares information (data) inputted therein, for example, the column and row addresses which may be under the control of an address multiplex system, with that programmed in the programmable elements of the comparing circuit. On the basis of this comparison, an appropriate defect recovery is effected.

    摘要翻译： 半导体存储器具有冗余电路的缺陷恢复方案。 存储器中的存储器阵列具有多个字线，多个位线，备用位线和多个存储器单元。 冗余电路包括具有可编程元件的一个或多个比较电路，其作为用于在其中存储存在于存储器阵列中的缺陷地址的存储器。 冗余电路的可编程元件可以根据多种不同类型的缺陷模式中的任何一种进行编程。 冗余电路的每个比较电路将在其中输入的信息（数据），例如可能在地址多路复用系统的控制下的列和行地址与在比较电路的可编程元件中编程的信息（数据）进行比较。 在此比较的基础上，进行适当的缺陷恢复。