公开(公告)号：US20120038006A1

公开(公告)日：2012-02-16

申请号：US12937652

申请日：2010-07-25

申请人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo ,  Qiagqing Liang

发明人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo ,  Qiagqing Liang

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/66636 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785

摘要： The present application discloses a semiconductor device comprising a fin of semiconductive material formed from a semiconductor layer over a semiconductor substrate and having two opposing sides perpendicular to the main surface of the semiconductor substrate; a source region and a drain region provided in the semiconductor substrate adjacent to two ends of the fin and being bridged by the fin; a channel region provided at the central portion of the fin; and a stack of gate dielectric and gate conductor provided at one side of the fin, where the gate conductor is isolated from the channel region by the gate dielectric, and wherein the stack of gate dielectric and gate conductor extends away from the one side of the fin in a direction parallel to the main surface of the semiconductor substrate, and insulated from the semiconductor substrate by an insulating layer. The semiconductor device has an improved short channel effect and a reduced parasitic capacitance and resistance, which contributes to an improved electrical property and facilitates scaling down of the transistor.

摘要翻译： 本申请公开了一种半导体器件，其包括由半导体衬底上的半导体层形成并具有垂直于半导体衬底的主表面的两个相对侧的半导体材料的鳍; 源极区域和漏极区域，设置在所述半导体衬底中，邻近所述鳍片的两端并被所述鳍片桥接; 设置在所述翅片的中央部的通道区域; 以及设置在鳍的一侧的栅极电介质和栅极导体的堆叠，其中栅极导体通过栅极电介质与沟道区隔离，并且其中栅极电介质和栅极导体的堆叠远离 翅片在平行于半导体衬底的主表面的方向上，并且通过绝缘层与半导体衬底绝缘。 半导体器件具有改善的短沟道效应和减小的寄生电容和电阻，这有助于改善电性能并且有助于晶体管的缩小。

公开(公告)号：US20120013009A1

公开(公告)日：2012-01-19

申请号：US12996721

申请日：2010-07-14

申请人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

发明人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/76808 ,  H01L21/76831 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a semiconductor substrate, a local interconnect structure connected to the semiconductor substrate, and at least one via stack structure electrically connected to the local interconnect structure, wherein the at least one via stack structure comprises a via having an upper via and a lower via, the width of the upper via being greater than that of the lower via; a via spacer formed closely adjacent to the inner walls of the lower via; an insulation layer covering the surfaces of the via and the via spacer; a conductive plug formed within the space surrounded by the insulation layer, and electrically connected to the local interconnect structure. The present invention is applicable to manufacture of a via stack in the filed of manufacturing semiconductor.

摘要翻译： 本发明公开了一种半导体结构及其制造方法。 半导体结构包括半导体衬底，连接到半导体衬底的局部互连结构以及电连接到局部互连结构的至少一个通孔堆叠结构，其中至少一个通孔堆叠结构包括具有上通孔和 下通孔，上通孔的宽度大于下通孔的宽度; 形成在靠近下通道的内壁的通孔间隔件; 覆盖通孔和通孔间隔物的表面的绝缘层; 形成在由所述绝缘层包围的空间内并且电连接到所述局部互连结构的导电插塞。 本发明可应用于半导体制造领域中的通孔叠层的制造。

公开(公告)号：US20110316080A1

公开(公告)日：2011-12-29

申请号：US12937486

申请日：2010-06-24

申请人： Zhijiong Luo ,  Huilong Zhu ,  Haizhou Yin

发明人： Zhijiong Luo ,  Huilong Zhu ,  Haizhou Yin

IPC分类号： H01L29/772 ,  H01L21/28

CPC分类号： H01L29/7851 ,  H01L29/66795

摘要： There is provided a fin transistor structure and a method of fabricating the same. The fin transistor structure comprises a fin formed on a semiconductor substrate, wherein an insulation material is formed between a portion of the fin serving as the channel region of the transistor structure and the substrate, and a bulk semiconductor material is formed between remaining portions of the fin and the substrate. Thereby, it is possible to reduce the current leakage while maintaining the advantages such as low cost and high heat transfer.

摘要翻译： 提供鳍式晶体管结构及其制造方法。 翅片晶体管结构包括形成在半导体衬底上的鳍片，其中在用作晶体管结构的沟道区域的鳍片的一部分和衬底之间形成绝缘材料，并且在半导体衬底的剩余部分之间形成体半导体材料 翅片和底物。 由此，可以在保持低成本，高热传递等优点的同时，减小电流泄漏。

公开(公告)号：US20110298018A1

公开(公告)日：2011-12-08

申请号：US12937502

申请日：2010-06-28

申请人： Haizhou Yin ,  Zhijiong Luo ,  Huilong Zhu

发明人： Haizhou Yin ,  Zhijiong Luo ,  Huilong Zhu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/4983 ,  H01L21/28105 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

摘要： The invention provides a transistor, including: a substrate having a channel region; a source region and a drain region on two ends of the channel region of the substrate respectively; a gate high-K dielectric layer on a top surface of the substrate above the channel region between the source region and the drain region; an interfacial layer under the gate high-K dielectric layer, including a first portion near the source region and a second portion near the drain region, wherein an equivalent oxide thickness of the first portion is larger than that of the second portion. An asymmetric replacement metal gate forms an asymmetric interfacial layer, which is thin at the drain region side and thick at the source region side. At the thin drain region side, the short channel effect is significant and the asymmetric interfacial layer advantageously suppresses the short channel effect. At the thick source region side, the carrier mobility has a large influence on the device, and the asymmetric interfacial layer prevents the carrier mobility from decreasing. Further, the asymmetric replacement metal gate implements an asymmetric metal work function.

摘要翻译： 本发明提供一种晶体管，包括：具有沟道区的衬底; 分别在所述衬底的沟道区域的两端上的源极区域和漏极区域; 位于源极区域和漏极区域之间的沟道区域上方的衬底顶表面上的栅极高K电介质层; 在栅极高K电介质层下面的界面层，包括靠近源区的第一部分和靠近漏极区的第二部分，其中第一部分的等效氧化物厚度大于第二部分的等效氧化物厚度。 不对称替代金属栅极形成不对称界面层，其在漏极区侧较薄，在源极区侧较厚。 在薄漏极侧，短沟道效应显着，不对称界面层有利地抑制了短沟道效应。 在较厚的源极侧，载流子迁移率对器件的影响较大，不对称界面层阻止载流子迁移率降低。 此外，不对称替代金属栅极实现了非对称金属功能。

公开(公告)号：US20110291184A1

公开(公告)日：2011-12-01

申请号：US13062911

申请日：2010-09-26

申请人： Haizhou Yin ,  Zhijiong Luo ,  Huilong Zhu

发明人： Haizhou Yin ,  Zhijiong Luo ,  Huilong Zhu

IPC分类号： H01L29/78 ,  H01L21/336 ,  B82Y99/00

CPC分类号： H01L29/78687 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66772

摘要： The present application discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a semiconductor substrate; an epitaxial semiconductor layer formed on two side portions of the semiconductor substrate; a gate stack formed at a central position on the semiconductor substrate and abutting the epitaxial semiconductor layer, the gate comprising a gate conductor layer and a gate dielectric layer which is sandwiched between the gate conductor layer and the semiconductor substrate and surrounding the lateral surfaces of the gate conductor layer; and a sidewall spacer formed on the epitaxial semiconductor layer and surrounding the gate. The method for manufacturing the above semiconductor structure comprises forming raised source/drain regions in the epitaxial semiconductor layer utilizing the sacrificial gate. The semiconductor structure and the method for manufacturing the same can simplify the fabrication process for an ultra-thin SOI transistor and reduce the ON-state resistance and power consumption of the transistor.

摘要翻译： 本申请公开了一种半导体结构及其制造方法。 半导体结构包括半导体衬底; 形成在所述半导体衬底的两个侧面上的外延半导体层; 形成在所述半导体衬底上的中心位置并与所述外延半导体层邻接的栅极叠层，所述栅极包括栅极导体层和栅极电介质层，所述栅极介电层夹在所述栅极导体层和所述半导体衬底之间， 栅极导体层; 以及形成在外延半导体层上并围绕栅极的侧壁间隔物。 制造上述半导体结构的方法包括利用牺牲栅极在外延半导体层中形成凸起的源/漏区。 半导体结构及其制造方法可以简化超薄SOI晶体管的制造工艺，并降低晶体管的导通电阻和功耗。

公开(公告)号：US20110260258A1

公开(公告)日：2011-10-27

申请号：US13063731

申请日：2010-06-22

申请人： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

发明人： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/7845

摘要： The devices are manufactured by replacement gate process and replacement sidewall spacer process, and both tensile stress in the channel region of NMOS device and compressive stress in the channel region of PMOS device are increased by forming a first stress layer with compressive stress in the space within the first metal gate layer of NMOS and a second stress layer with tensile stress in the space within the second metal gate layer of PMOS, respectively. After formation of the stress layers, sidewall spacers of the gate stacks of PMOS and NMOS devices are removed so as to release stress in the channel regions. In particular, stress structure with opposite stress may be formed on sidewalls of the gate stacks of the NMOS device and PMOS device and on a portion of the source region and the drain region, in order to further increase both tensile stress of the NMOS device and compressive stress of the PMOS device.

摘要翻译： 器件通过更换栅极工艺和替换侧壁间隔工艺制造，NMOS器件的沟道区域中的拉伸应力和PMOS器件的沟道区域中的压应力均增加，在第一应力层内形成压缩应力 NMOS的第一金属栅极层和在PMOS的第二金属栅极层内的空间中具有拉伸应力的第二应力层。 在形成应力层之后，去除PMOS和NMOS器件的栅叠层的侧壁间隔物，以释放沟道区中的应力。 特别地，具有相反应力的应力结构可以形成在NMOS器件和PMOS器件的栅极堆叠的侧壁上，并且在源极区域和漏极区域的一部分上形成，以便进一步增加NMOS器件的拉伸应力和 PMOS器件的压应力。

公开(公告)号：US20110169088A1

公开(公告)日：2011-07-14

申请号：US12686402

申请日：2010-01-13

申请人： Huilong Zhu ,  Zhijiong Luo ,  Qingqing Liang ,  Haizhou Yin

发明人： Huilong Zhu ,  Zhijiong Luo ,  Qingqing Liang ,  Haizhou Yin

IPC分类号： H01L27/12 ,  H01L21/762

CPC分类号： H01L27/1207 ,  H01L21/76251 ,  H01L21/8221 ,  H01L27/0688 ,  H01L29/66545

摘要： A device and method is provided that in one embodiment provides a first semiconductor device including a first gate structure on a first channel region, in which a first source region and a first drain region are present on opposing sides of the first channel region, in which a metal nitride spacer is present on only one side of the first channel region. The device further includes a second semiconductor device including a second gate structure on a second channel region, in which a second source region and a second drain region are present on opposing sides of the second channel region. Interconnects may be present providing electrical communication between the first semiconductor device and the second semiconductor device, in which at least one of the first semiconductor device and the second semiconductor device is inverted. A structure having a reverse halo dopant profile is also provided.

摘要翻译： 提供了一种装置和方法，在一个实施例中提供了第一半导体器件，其包括在第一沟道区上的第一栅极结构，其中第一源区和第一漏区存在于第一沟道区的相对侧上，其中 金属氮化物间隔物仅存在于第一沟道区的一侧。 该器件还包括在第二沟道区上包括第二栅极结构的第二半导体器件，其中第二源区和第二漏区存在于第二沟道区的相对侧上。 可以存在互连件，其提供第一半导体器件和第二半导体器件之间的电连通，其中第一半导体器件和第二半导体器件中的至少一个被反转。 还提供了具有反向卤素掺杂剂分布的结构。

公开(公告)号：US07741658B2

公开(公告)日：2010-06-22

申请号：US11842437

申请日：2007-08-21

申请人： Yaocheng Liu ,  Zhijiong Luo ,  Huilong Zhu

发明人： Yaocheng Liu ,  Zhijiong Luo ,  Huilong Zhu

IPC分类号： H01L31/0328

CPC分类号： H01L21/26506 ,  H01L21/268 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

摘要： The embodiments of the invention comprise a self-aligned super stressed p-type field effect transistor (PFET). More specifically, a field effect transistor comprises a channel region comprising N-doped material and a gate above the channel region. The field effect transistor also includes a source region on a first side of the channel region and a drain region on a second side of the channel region opposite the first side. The source and drain regions each comprise silicon germanium, wherein the silicon germanium has structural indicia of epitaxial growth.

摘要翻译： 本发明的实施例包括自对准超应力p型场效应晶体管（PFET）。 更具体地，场效应晶体管包括包含N掺杂材料的沟道区和沟道区上方的栅。 场效应晶体管还包括在沟道区的第一侧上的源极区域和与第一侧相对的沟道区域的第二侧上的漏极区域。 源极和漏极区域各自包含硅锗，其中硅锗具有外延生长的结构标记。

公开(公告)号：US07691690B2

公开(公告)日：2010-04-06

申请号：US11622586

申请日：2007-01-12

申请人： Huilong Zhu ,  Zhijiong Luo

发明人： Huilong Zhu ,  Zhijiong Luo

IPC分类号： H01L21/00

CPC分类号： H01L29/66795 ,  H01L29/785

摘要： Methods for forming fully silicided gates over fins of FinFet devices are disclosed. The disclosure provides methods for patterning a gate stack over each fin from a polysilicon layer and a polysilicon germanium layer, and then removing the polysilicon germanium layer over one of the fins. The disclosure further includes forming a metal layer over both fins and annealing the FinFet device to form fully silicided gates over each fin of the FinFet device.

摘要翻译： 公开了在FinFet装置的翅片上形成完全硅化栅的方法。 本公开提供了用于从多晶硅层和多晶硅锗层在每个鳍上形成栅叠层的方法，然后在一个鳍上去除多晶硅锗层。 本公开还包括在两个翅片上形成金属层并退火FinFet器件以在FinFet器件的每个鳍上形成完全硅化的栅极。

公开(公告)号：US07646039B2

公开(公告)日：2010-01-12

申请号：US11830972

申请日：2007-07-31

申请人： Huilong Zhu ,  Zhijiong Luo ,  Qingqing Liang

发明人： Huilong Zhu ,  Zhijiong Luo ,  Qingqing Liang

IPC分类号： H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/0336

CPC分类号： H01L29/7843 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/205 ,  H01L29/26 ,  H01L29/267 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/7835 ,  H01L29/78654

摘要： A source trench and a drain trench are asymmetrically formed in a top semiconductor layer comprising a first semiconductor in a semiconductor substrate. A second semiconductor material having a narrower band gap than the first semiconductor material is deposited in the source trench and the drain trench to form a source side narrow band gap region and a drain side narrow band gap region, respectively. A gate spacer is formed and source and drain regions are formed in the top semiconductor layer. A portion of the boundary between an extended source region and an extended body region is formed in the source side narrow band gap region. Due to the narrower band gap of the second semiconductor material compared to the band gap of the first semiconductor material, charge formed in the extended body region is discharged through the source and floating body effects are reduced or eliminated.

摘要翻译： 源极沟槽和漏极沟槽在包括半导体衬底中的第一半导体的顶部半导体层中不对称地形成。 在源极沟槽和漏极沟槽中沉积具有比第一半导体材料窄的带隙的第二半导体材料，以分别形成源极窄带隙区域和漏极侧窄带隙区域。 形成栅极间隔物，并且在顶部半导体层中形成源区和漏极区。 扩展源极区域和延伸体区域之间的边界的一部分形成在源极窄带隙区域中。 由于与第一半导体材料的带隙相比，第二半导体材料的带隙较窄，所以形成在扩展体区域中的电荷通过源放电，并且减少或消除浮体效应。