公开(公告)号：US5708601A

公开(公告)日：1998-01-13

申请号：US602237

申请日：1996-02-16

Applicant: Vernon G. McKenny ,  Luigi Pascucci ,  Marco Maccarrone

Inventor： Vernon G. McKenny ,  Luigi Pascucci ,  Marco Maccarrone

IPC: G11C29/00 ,  G11C7/00

CPC classification number: G11C29/835

Abstract: An apparatus identifies redundancy memory cells that are selected to replace defective memory cells of a memory matrix that communicates with a data bus. A redundancy address register is associated with one of the redundancy memory cells. The redundancy address register stores a default state until it is programmed with an address of one of the defective memory cells. A control circuit generates a test signal during an identification mode. A detect circuit is coupled to the control circuit and to the redundancy address register and generates a default-detect signal in response to the test signal when the redundancy address register contains the default state. A data-bus multiplexer that is coupled to the redundancy-cell selection circuit, the data bus, and the control circuit couples the default detect signal to the data bus in response to the test signal.

Abstract translation: 一种装置识别被选择来替换与数据总线通信的存储器矩阵的有缺陷的存储单元的冗余存储单元。 冗余地址寄存器与冗余存储单元之一相关联。 冗余地址寄存器存储默认状态，直到用一个缺陷存储单元的地址编程为止。 控制电路在识别模式期间产生测试信号。 检测电路耦合到控制电路和冗余地址寄存器，并且当冗余地址寄存器包含默认状态时，响应于测试信号产生默认检测信号。 耦合到冗余单元选择电路，数据总线和控制电路的数据总线复用器响应于测试信号将默认检测信号耦合到数据总线。

公开(公告)号：US5703821A

公开(公告)日：1997-12-30

申请号：US562736

申请日：1995-11-27

Applicant: Andrea Baroni ,  Giovanni Mastrodomenico ,  Michele Taliercio ,  Piero Capocelli ,  Luigi Carro ,  Rajamohan Varambally

Inventor： Andrea Baroni ,  Giovanni Mastrodomenico ,  Michele Taliercio ,  Piero Capocelli ,  Luigi Carro ,  Rajamohan Varambally

IPC: G06F17/50 ,  G11C7/14 ,  G11C7/22 ,  G11C7/00

CPC classification number: G11C7/22 ,  G11C7/14

Abstract: A single-port RAM generator architecture, for the generation of different RAM structures in a CAD environment, and to test the operation capabilities of the different RAM structure, The architecture includes a Static RAM matrix and a self timed architecture, which includes a control logic, both a dummy row and a dummy column having respectively equivalent load of a word line and of bit column of said matrix. The dummy column is discharged at a faster rate than the corresponding bit column optimizing the timing and reducing power consumption. Different column multiplexer selections provide different RAMs for a selected RAM size, each having slightly different silicon area and timing performance.

Abstract translation: 单端口RAM生成器架构，用于在CAD环境中生成不同的RAM结构，并测试不同RAM结构的操作能力。该架构包括一个静态RAM矩阵和一个自定时架构，其中包括一个控制逻辑 ，具有分别具有所述矩阵的字线和位列的等效负载的虚拟行和虚拟列。 虚拟列以比相应位列更快的速率放电，优化定时并降低功耗。 不同的列复用器选择为选定的RAM大小提供不同的RAM，每个RAM具有略微不同的硅面积和时序性能。

公开(公告)号：US5696404A

公开(公告)日：1997-12-09

申请号：US527763

申请日：1995-09-13

Applicant: Bruno Murari ,  Roberto Toscani ,  Fabio Marchio ,  Sandro Storti

Inventor： Bruno Murari ,  Roberto Toscani ,  Fabio Marchio ,  Sandro Storti

IPC: H01L21/66 ,  G01R31/28 ,  H01L21/822 ,  H01L23/58 ,  H01L27/02 ,  H01L27/04 ,  H05K1/02 ,  H05K1/03 ,  H05K3/00 ,  H01L23/62 ,  H01L29/00

CPC classification number: H01L22/32 ,  G01R31/2884 ,  H01L27/0207 ,  G01R31/2831 ,  H01L2224/05554 ,  H05K1/0266 ,  H05K1/0306 ,  H05K3/0097

Abstract: A manufacturing method for fabricating integrated electronic circuits on a semiconductor support provides a plurality of integrated circuits and provides a plurality of scribing lines. The scribing lines are located such that the electronic circuits are regularly spaced apart by the scribing lines. A network of electrical connection lines is provided in at least one of the scribing lines. Metallization strips are provided in the scribing lines as electrical connection lines, and the electrical connection lines are connected to the integrated circuit. At least one current limitation element is provided between the electrical connection line and the integrated circuit. In this manner it is possible to simultaneously perform electrical testing of all the circuits present on the same wafer.

Abstract translation: 在半导体支架上制造集成电子电路的制造方法提供多个集成电路并提供多条划线。 划线被定位成使得电子电路通过划线生长规则地间隔开。 在至少一个划线上提供电连接线的网络。 金属化带在划线中作为电连接线设置，并且电连接线连接到集成电路。 在电连接线和集成电路之间提供至少一个电流限制元件。 以这种方式，可以同时对同一晶片上存在的所有电路进行电测试。

公开(公告)号：US5687135A

公开(公告)日：1997-11-11

申请号：US700126

申请日：1996-08-20

Applicant: Marco Olivo ,  Marco Maccarrone

Inventor： Marco Olivo ,  Marco Maccarrone

IPC: G11C8/04 ,  G11C16/06 ,  H03K21/00 ,  G11C8/00

CPC classification number: H03K21/00 ,  G11C16/06 ,  G11C8/04

Abstract: A count unit for performing a number of count operations and wherein, instead of a counter for each count function, provision is made for one counter and a number of registers equal in number to the count functions involved. The registers store the preceding count value and, when their content is to be incremented or in any way altered, load it into the counter which provides for performing the required operation, at the end of which, the content of the counter is stored in the respective register. One of the registers presents a second parallel input for externally loading an initial data which may be transferred to the other registers via the counter.

Abstract translation: 用于执行多个计数操作的计数单元，并且其中，代替每个计数功能的计数器，提供一个计数器和与所涉及的计数功能相等数量的寄存器数量。 寄存器存储上述计数值，当其内容要增加或以任何方式更改时，将其加载到计数器中，该计数器用于执行所需的操作，最后计数器的内容存储在 各自的登记册。 其中一个寄存器提供第二个并行输入，用于外部加载初始数据，初始数据可以通过计数器传输到其他寄存器。

公开(公告)号：US5677871A

公开(公告)日：1997-10-14

申请号：US688233

申请日：1996-07-29

Applicant: Federico Pio ,  Carlo Riva ,  Silvia Lucherini

Inventor： Federico Pio ,  Carlo Riva ,  Silvia Lucherini

IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11526 ,  G11C16/04 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11541

Abstract: A circuit structure for a matrix of EEPROM memory cells, being of a type which comprises a matrix of cells including plural rows and columns, with each row being provided with a word line and a control gate line and each column having a bit line; the bit lines, moreover, are gathered into groups or bytes of simultaneously addressable adjacent lines. Each cell in the matrix incorporates a floating gate transistor which is coupled to a control gate, connected to the control gate line, and is connected serially to a selection transistor; also, the cells of each individual byte share their respective source areas, which areas are structurally independent for each byte and are led to a corresponding source addressing line extending along a matrix column.

Abstract translation: 一种用于EEPROM存储器单元的矩阵的电路结构，其包括包括多行和列的单元矩阵，每行具有字线和控制栅极线，每列具有位线; 此外，位线被收集成同时可寻址的相邻线的组或字节。 矩阵中的每个单元都包含一个浮动栅极晶体管，它连接到控制栅极，连接到控制栅极线，并串联连接到选择晶体管; 每个单独字节的单元也共享它们各自的源区域，哪些区域对于每个字节在结构上是独立的，并且被引导到沿着矩阵列延伸的对应的源寻址行。

公开(公告)号：US5661430A

公开(公告)日：1997-08-26

申请号：US529805

申请日：1995-09-19

Applicant: Sergio Palara ,  Raffaele Zambrano

Inventor： Sergio Palara ,  Raffaele Zambrano

IPC: H01L27/04 ,  H01L27/02 ,  H01L29/78 ,  H03K17/08 ,  H03K17/687 ,  H03K17/16

CPC classification number: H01L27/0248

Abstract: An integrated circuit including a power stage, a low-voltage component separated from the power stage by an isolating region and a reference potential region at a reference potential. The power stage includes an N-type substrate region which may be biased to a terminal voltage with respect to the reference potential and the isolating region has P-type conductivity. The low-voltage component includes an N-type input region receiving an input voltage. The input voltage and the terminal voltage may oscillate a few tens of volts above or below the reference potential and turn on parasitic transistors. To prevent turning on of the parasitic transistors, switchable conductive paths are interposed between the isolating region on the one hand, and the substrate region, the input region and the reference potential region on the other, for electrically connecting the isolating region to one of the substrate region, input region and reference potential region which presents instant by instant the lowest potential.

Abstract translation: 一种集成电路，包括功率级，通过隔离区与功率级分离的低电压分量和参考电位的参考电位区。 功率级包括可以相对于参考电位偏置到端电压的N型衬底区域，并且隔离区域具有P型导电性。 低电压分量包括接收输入电压的N型输入区域。 输入电压和端子电压可能会振荡高于或低于参考电位几十伏，并接通寄生晶体管。 为了防止寄生晶体管的导通，可切换的导电路径一方面插入在隔离区域与另一方面的衬底区域，输入区域和参考电势区域之间，用于将隔离区域电连接到 衬底区域，输入区域和参考电位区域，其立即呈现最低电位。

公开(公告)号：USRE35588E

公开(公告)日：1997-08-19

申请号：US296205

申请日：1994-08-25

Applicant: Silvano Gornati ,  Mauro Merlo ,  Maurizio Zuffada ,  Loic Lietar

Inventor： Silvano Gornati ,  Mauro Merlo ,  Maurizio Zuffada ,  Loic Lietar

IPC: G09G1/04 ,  G09G1/12 ,  G09G1/16 ,  H04N3/27 ,  H04N5/46 ,  H01J29/70 ,  H01J29/72

CPC classification number: G09G1/167 ,  G09G1/04 ,  G09G1/16

Abstract: A broad operational range, automatic device for the change of frequency in the horizontal deflection of multi-synchronization monitors comprises an integrated circuit incorporating,a frequency meter being input and analog synchronization signal.a phase comparator having two inputs and in turn receiving said synchronization signal on one input,a voltage-controlled oscillator adapted to output a signal whose frequency is depending on said voltage and operatively linked to an output of said phase comparator, anda counter connected with its input, on the one side, to the oscillator output, and on the other side, to the meter output, said counter having an output connected to the other input of the phase comparator also forming the integrated circuit output.

Abstract translation: 用于在多同步监视器的水平偏转中改变频率的广泛的操作范围包括集成了输入的频率计和模拟同步信号的集成电路。 相位比较器，具有两个输入端，并在一个输入端接收所述同步信号;压控振荡器，其适于输出其频率取决于所述电压并可操作地连接到所述相位比较器的输出端的信号，以及与 其一端的输入到振荡器输出，另一方面输入到仪表输出，所述计数器具有连接到相位比较器的另一输入端的输出端，也形成集成电路输出。

公开(公告)号：US5659509A

公开(公告)日：1997-08-19

申请号：US391999

申请日：1995-02-16

Applicant: Carla Maria Golla ,  Marco MacCarrone

Inventor： Carla Maria Golla ,  Marco MacCarrone

IPC: G11C29/00 ,  G11C29/04

CPC classification number: G11C29/789

Abstract: A method for programming non-volatile row redundancy memory registers. Each register is associated with a respective pair of redundancy row and each one programmable to store in two subsets of a set of memory cells a pair of addresses of a respective pair of adjacent defective rows. Each memory register is supplied with row address signals and with a respective selection signal belonging to a set of column address signals. The method provides for: applying to the row address lines the address of a first defective row of the pair of adjacent defective rows; activating one of the selection signals for selecting the register which is to be programmed; applying to a further column address line a first logic level to select for programming in the selected memory register, a first subset of memory cells; enabling the programming of the address of the first defective row of the pair of adjacent defective rows into the first subset of memory cells; applying to at least a subset of the row address lines the address of the second defective row of the pair; applying to the further column line a second, opposite logic level to select for programming, in the selected memory register, at least a group of memory cells of the second subset of the two subsets of memory cells; and enabling the programming of the address of the second defective row of the pair of adjacent defective rows into the second subset of memory cells.

Abstract translation: 一种用于编程非易失性行冗余存储器寄存器的方法。 每个寄存器与相应的一对冗余行相关联，并且每个寄存器可编程以在一组存储器单元的两个子集中存储相应的一对相邻有缺陷行的一对地址。 每个存储器寄存器被提供有行地址信号和属于一组列地址信号的相应选择信号。 该方法提供：向行地址线应用该对相邻的有缺陷行的第一缺陷行的地址; 激活用于选择要编程的寄存器的选择信号之一; 向另一列地址线施加第一逻辑电平以选择用于在选择的存储器寄存器中编程存储器单元的第一子集; 使得能够将一对相邻的有缺陷行的第一缺陷行的地址编程到存储器单元的第一子集中; 向所述行地址线的至少一个子集施加所述对的所述第二缺陷行的地址; 在所选择的存储器寄存器中向所述另外的列线施加第二相反逻辑电平以选择用于在所述存储器单元的所述两个子集中的所述第二子集的至少一组存储器单元中进行编程; 并且使得能够将该对相邻的有缺陷行的第二有缺陷行的地址编程到存储器单元的第二子集中。

公开(公告)号：US5659502A

公开(公告)日：1997-08-19

申请号：US665862

申请日：1996-06-19

Applicant: Mauro Sali ,  Corrado Villa ,  Marcello Carrera

Inventor： Mauro Sali ,  Corrado Villa ,  Marcello Carrera

IPC: G11C17/00 ,  G11C16/06 ,  G11C16/30 ,  G11C13/00

CPC classification number: G11C16/30

Abstract: A negative word line voltage regulation circuit integratable in an electrically erasable semiconductor memory device. The circuit regulates a negative word line voltage to be supplied to word lines of the memory device during an electrical erasure of the memory device. The circuit includes an operational amplifier with a first input coupled to a reference voltage, a second input coupled to the negative word line voltage, and an output controlling a voltage regulation branch connected between an external power supply and the negative word line voltage, to provide a regulation current for regulating the negative word line voltage. The output of the operational amplifier also controls a voltage sensing branch, connected between the external power supply and the negative word line voltage, to provide a sensing signal coupled to the second input of the operational amplifier.

Abstract translation: 可在电可擦除半导体存储器件中集成的负字线电压调节电路。 电路在存储器件的电擦除期间调节要提供给存储器件的字线的负字线电压。 电路包括具有耦合到参考电压的第一输入的运算放大器，耦合到负字线电压的第二输入，以及控制连接在外部电源和负字线电压之间的电压调节支路的输出，以提供 用于调节负字线电压的调节电流。 运算放大器的输出还控制连接在外部电源和负字线电压之间的电压感测支路，以提供耦合到运算放大器的第二输入端的感测信号。

公开(公告)号：USRE35582E

公开(公告)日：1997-08-12

申请号：US606870

申请日：1996-02-26

Applicant: Angelo Pariani ,  Walter Rossi ,  Vanni Saviotti

Inventor： Angelo Pariani ,  Walter Rossi ,  Vanni Saviotti

IPC: H04M19/00 ,  H04M1/00

CPC classification number: H04M19/005

Abstract: A method of lowering the power absorbed by an interface circuit, in the "power-down" state thereof, as incorporated to a telephone exchange and connected to a telephone subscriber line, being of a type which comprises a monitoring circuit portion connected between the line and the exchange. The method involves the steps of,detecting the polarization level of a conductor in the line,comparing that level with a reference value by means of a comparator having an input connected to the line and an output connected to the input of the monitoring circuit portion,switching the interface circuit to a standby state on a higher level than the reference value being sensed,once again detecting the polarization level of the line, this time through the interface circuit, andactivating the telephone exchange when, on completion of the second detection step, the polarization level stays above the reference value.

Abstract translation: 一种降低由接口电路吸收的功率的方法，其在其“断电”状态下，并入电话交换机并连接到电话用户线路，其类型包括连接在线路之间的监视电路部分 和交流。 该方法包括以下步骤：检测线路中的导体的极化电平，通过具有连接到该线路的输入的比较器和连接到监视电路部分的输入端的输出端将该电平与基准值进行比较， 将接口电路切换到比所感测的参考值更高的待机状态，再次通过接口电路检测线路的极化电平，并且在第二检测步骤完成时激活电话交换机 ，极化水平保持高于参考值。