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61.发明公开公开(公告)号：US20240327203A1
公开(公告)日：2024-10-03
申请号：US18613746
申请日：2024-03-22
Applicant: STMicroelectronics International N.V.
Inventor： Mark Andrew SHAW , Fabio QUAGLIA , Domenico GIUSTI , Marco FERRERA
CPC classification number: B81B7/007 , B81B3/007 , B81C1/00301 , B81C1/00658 , H01L25/18 , H10N39/00 , B81B2201/0271 , B81B2203/0127 , B81B2207/012 , B81B2207/096 , B81C2203/0792
Abstract: A method for manufacturing a MEMS device includes forming a first solid body by forming, on a substrate, a layered structure having a thickness of a value comprised between 4 and 10 μm, with the layered structure having a first surface that is uniformly flat or planar throughout the extension thereof that faces the substrate. The method further includes forming, on a second surface of the layered structure opposite to the first surface in a direction, multiple transducer devices. The method then proceeds with coupling the first solid body to a supporting structure, and completely removing the substrate to expose said uniformly flat or planar surface.
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公开(公告)号：US12105145B2
公开(公告)日：2024-10-01
申请号：US18362550
申请日：2023-07-31
Applicant: STMicroelectronics International N.V.
Inventor： Sandeep Jain , Shalini Pathak
IPC: G01R31/3185 , G01R31/317 , G01R31/3183
CPC classification number: G01R31/318536 , G01R31/317 , G01R31/318335 , G01R31/31853 , G01R31/318533 , G01R31/318555 , G01R31/318558 , G01R31/318566
Abstract: A method for testing a chip comprising receiving N scan-in chains of test data; using the N scan-in chains of test data to perform tests on the chip; receiving a merged expected test-result and masking-instruction signal on X pins of the chip from the off-chip test equipment, X being less than 2*N; decoding the merged expected test-result and masking-instruction signal to extract N decoded output signals, each of the N decoded output signals corresponding to a respective chain of test results.
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公开(公告)号：US20240321809A1
公开(公告)日：2024-09-26
申请号：US18601216
申请日：2024-03-11
Applicant: STMicroelectronics International N.V.
Inventor： Romain COFFY , David AUCHERE , Vipin VELAYUDHAN
IPC: H01L23/00
CPC classification number: H01L24/32 , H01L24/27 , H01L24/29 , H01L2224/27318 , H01L2224/2741 , H01L2224/29144 , H01L2224/29155 , H01L2224/32227 , H01L2224/32238 , H01L2924/151
Abstract: An integrated circuit chip is bonded to a support. The chip includes a first connection pad and two second connection pads. The support includes a third connection pad and two fourth connection pads. A stack layers includes first, second, and third conductive layers and insulating layers. The first, second, and third conductive layers are separated from one another by the insulating layers. The second conductive layer is positioned between the first and third conductive layers. The first and third conductive layers electrically connect the two second connection pads to the two fourth connection pads. The second conductive layer electrically connects the first connection pad to the third connection pad.
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公开(公告)号：US20240312495A1
公开(公告)日：2024-09-19
申请号：US18676354
申请日：2024-05-28
Applicant: STMicroelectronics International N.V.
Inventor： Vikas RANA , Arpit VIJAYVERGIA
Abstract: The present disclosure is directed to arranging user data memory cells and test memory cells in a configurable memory array that can perform both differential and single ended read operations during memory start-up and normal memory use, respectively. Different arrangements of the user data memory cells and the test memory cells in the memory array result in increased effectiveness of memory array, in terms of area optimization, memory read accuracy and encryption for data security.
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公开(公告)号：US20240311227A1
公开(公告)日：2024-09-19
申请号：US18122420
申请日：2023-03-16
Applicant: STMicroelectronics International N.V.
Inventor： Avneep Kumar Goyal , Thomas Szurmant
CPC classification number: G06F11/0793 , G06F1/08 , G06F11/0745
Abstract: According to an embodiment, a system is provided that includes a debugging tool and an application board. The debugging tool includes a serial wire debug (SWD) host coupled to a single signal debug port (SSDP) host. The application board includes an SWD target coupled to an SSDP target. The SWD target is configured to communicate SWD signals with the SWD host. The SSDP target is configured to encode the SWD signals to SSDP signals for communication over a Controller Area Network (CAN) Bus between the application board and the debugging tool. The SSDP signals are pulse-width modulation (PWM) encoded signals of the SWD signals. An SWD clock signal generated by the SWD host is the carrier signal for the PWM encoded signals. The SSDP target is configured to decode the SSDP signals received from the SSDP host over the CAN Bus to the SWD signals.
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Patent Agency Ranking
公开(公告)号：US12095601B2
公开(公告)日：2024-09-17
申请号：US18064593
申请日：2022-12-12
Applicant: STMicroelectronics International N.V.
Inventor： Andrea Mineo , Giovanni Amedeo Cirillo
IPC: H04L27/06
CPC classification number: H04L27/06
Abstract: According to an embodiment, a circuit for decoding a biphase mark coding (BMC) encoded signal is provided. The circuit includes a matched filter, a decoder circuit and a finite state machine (FSM) circuit. The matched filter is configured to generate a first response and a second response to the BMC encoded signal. The first response and second response operate respectively, at a half clock period and a full clock period of the BMC encoded signal. The detector circuit is coupled to an output of the matched filter. The detector circuit is configured to generate an output signal based on detecting a half-bit rise for the first response, a half-bit fall for the first response, a full-bit rise for the second response, or a full-bit fall for the second response. The FSM circuit is configured to decode the BMC encoded signal based on the output signal of the detector circuit.
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公开(公告)号：US20240305197A1
公开(公告)日：2024-09-12
申请号：US18597428
申请日：2024-03-06
Applicant: STMicroelectronics International N.V.
Inventor： David CHESNEAU
IPC: H02M3/158
CPC classification number: H02M3/158
Abstract: A buck switching converter is calibrated using a method which alternates between first and second calibration phases. During each first calibration phase: a time period of low-side switch on state is kept constant and, for each current pulse in an inductor, a sign of a value of the current at the end of the time period of on state of the low-side switch is determined. Modification of a time period of high-side switch on state is made based on the determined sign. During each second calibration phase: a time period of high-side switch on state is kept constant and, for each current pulse in the inductor, a value of the current at the end of the time period of on state of the high-side switch is compared with a target value. Modification of the time period of low-side switch on state is made based on the comparison.
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公开(公告)号：US20240304731A1
公开(公告)日：2024-09-12
申请号：US18594210
申请日：2024-03-04
Applicant: STMicroelectronics International N.V.
Inventor： Francois TAILLIET , Marc BATTISTA
IPC: H01L29/8605 , H01L27/06
CPC classification number: H01L29/8605 , H01L27/0629
Abstract: An electronic device includes first and second diffused resistors in contact with each other to form a PN junction. The device is configured so that a potential difference between the first and second resistors is constant at any point of the PN junction. The PN junction is reverse-biased.
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公开(公告)号：US20240304224A1
公开(公告)日：2024-09-12
申请号：US18583568
申请日：2024-02-21
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Christophe GONCALVES , Marc BATTISTA , Francois TAILLIET
CPC classification number: G11C7/08 , G11C7/1048 , G11C7/1069
Abstract: The present disclosure relates to a method of reading a word in a memory device, wherein the word is comprised in a first set of words that can be read by the memory device, each word of the first set comprising at least one byte of data, each word being contained in memory cells, the method comprising a pre-charging step during which the first set and at least a second set of words are pre-charged, a first terminal of each cell of the first and second sets being floating during the pre-charging step.
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公开(公告)号：US12088326B2
公开(公告)日：2024-09-10
申请号：US17940236
申请日：2022-09-08
Applicant: STMicroelectronics International N.V.
Inventor： Ankur Bal , Abhishek Jain
CPC classification number: H03M3/464 , H03K3/356 , H03M1/0626 , H03M3/43
Abstract: A continuous time, sigma-delta analog-to-digital converter circuit includes a sigma-delta modulator circuit configured to receive an analog input signal. A single bit quantizer of the modulator generates a digital output signal at a sampling frequency. A data storage circuit stores bits of the digital output signal and digital-to-analog converter (DAC) elements are actuated in response to the stored bits to generate an analog feedback signal for comparison to the analog input signal. A filter circuit includes polyphase signal processing paths and a summation circuit configured to sum outputs from the polyphase signal processing paths to generate a converted output signal. A fan out circuit selectively applies the stored bits from the data storage circuit to inputs of the polyphase signal processing paths of the filter circuit.
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