公开(公告)号：US09607998B2

公开(公告)日：2017-03-28

申请号：US15146299

申请日：2016-05-04

申请人： ROHM CO., LTD.

发明人： Yuichi Nakao

IPC分类号： H01L27/108 ,  H01L27/11507 ,  H01L21/768 ,  H01L27/11504 ,  H01L49/02 ,  H01L21/02 ,  H01L21/32

CPC分类号： H01L27/11507 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/32 ,  H01L21/76849 ,  H01L21/7687 ,  H01L27/11504 ,  H01L28/55 ,  H01L28/57 ,  H01L28/60 ,  H01L28/82

摘要： A semiconductor storage device includes an insulating layer. A ferroelectric capacitor is on the insulating layer and includes a lower electrode, a ferroelectric film, and an upper electrode. An interlayer insulating film is formed on the insulating layer, and has an opening where the ferroelectric capacitor is disposed. A first metal plug is formed in the insulating layer and connected to the lower electrode via the opening. A second metal plug is embedded in the insulating layer outside the ferroelectric capacitor. A hydrogen barrier film covers the ferroelectric capacitor and the interlayer insulating film. An upper surface of the interlayer insulating film is higher than an upper surface of the first metal plug so that a step is therebetween. The lower electrode is formed on the upper surface of the interlayer insulating film, the upper surface of the first metal plug and the step. The upper surface of the interlayer insulating film and the upper surface of the first metal plug are interlinked via a recessed portion of the interlayer insulating film.

公开(公告)号：US09318693B2

公开(公告)日：2016-04-19

申请号：US14010174

申请日：2013-08-26

申请人： CYPRESS SEMICONDUCTOR CORPORATION

发明人： John Cronin ,  Shan Sun ,  Thomas Davenport

IPC分类号： H01L21/00 ,  H01L43/02 ,  H01L27/115 ,  H01L27/22

CPC分类号： H01L43/02 ,  H01L27/11504 ,  H01L27/11507 ,  H01L27/228

摘要： A method for a non-volatile, ferroelectric random access memory (F-RAM) device that includes a ferroelectric capacitor aligned with a preexisting structure is described. In one embodiment, the method includes forming an opening in an insulating layer over a contact in a planar surface of a substrate to expose at least a portion of the contact. Next a self-aligned contact (SAC) is formed electrically coupling to the contact, the SAC medially located in the opening and proximal to a sidewall thereof. A ferroelectric spacer is then formed in the opening medially of the SAC, and a top electrode spacer formed in the opening over the insulating cap and medially of the ferroelectric spacer.

摘要翻译： 描述了一种包括与预先存在的结构对准的铁电电容器的非易失性铁电随机存取存储器（F-RAM）器件的方法。 在一个实施例中，该方法包括在基板的平坦表面中的接触件上方的绝缘层中形成开口，以暴露接触件的至少一部分。 接下来，自对准接触（SAC）形成为电耦合到接触件，SAC内侧位于开口中并且靠近其侧壁。 然后在SAC的中间的开口中形成铁电间隔物，以及形成在绝缘帽上的开口中的顶部电极间隔物，并且在铁电间隔物的中间。

公开(公告)号：US20150155288A1

公开(公告)日：2015-06-04

申请号：US14615455

申请日：2015-02-06

申请人： ROHM CO., LTD.

发明人： Yuichi NAKAO

IPC分类号： H01L27/115 ,  H01L49/02

CPC分类号： H01L27/11507 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/32 ,  H01L21/76849 ,  H01L21/7687 ,  H01L27/11504 ,  H01L28/55 ,  H01L28/57 ,  H01L28/60 ,  H01L28/82

摘要： A semiconductor-storage-device manufacturing method of the present invention is a method for manufacturing a semiconductor storage device provided with a ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode, and the method includes a step of embedding a first metal plug and a second metal plug in an insulating layer; a step of forming a covering layer that covers at least the second metal plug while securing a part that comes into electric contact with the first metal plug; a step of forming a deposit structure by sequentially depositing a material for the lower electrode, a material for the ferroelectric film, and a material for the upper electrode after forming the covering layer; and a step of forming the ferroelectric capacitor by etching and removing other parts except a part of the deposit structure such that the part of the deposit structure remains on the first metal plug.

摘要翻译： 本发明的半导体存储元件的制造方法是具有下电极，强电介质膜和上电极的强电介质电容器的半导体存储元件的制造方法，其特征在于，包括： 金属插塞和绝缘层中的第二金属插塞; 形成覆盖层的步骤，所述覆盖层至少覆盖所述第二金属插塞，同时确保与所述第一金属插塞电接触的部分; 在形成覆盖层之后，依次沉积下电极材料，铁电薄膜材料和上电极材料，形成沉积结构的步骤; 以及通过蚀刻除去所述沉积结构的一部分以外的其它部分使得所述沉积结构的所述部分保留在所述第一金属插塞上而形成所述强电介质电容器的步骤。

公开(公告)号：US20140362632A1

公开(公告)日：2014-12-11

申请号：US14466201

申请日：2014-08-22

申请人： Rohm Co., Ltd.

发明人： Yoshikazu Fujimori ,  Hiromitsu Kimura ,  Toshiyuki Kanaya ,  Daisuke Notsu

IPC分类号： G11C11/22

CPC分类号： G11C11/22 ,  G11C11/221 ,  H01L27/0207 ,  H01L27/11504 ,  H01L27/11507 ,  H01L27/11512 ,  H01L28/55 ,  H03K3/356008

摘要： A data holding device includes a loop structure unit configured to hold data using a plurality of logic gates connected in a loop shape, a nonvolatile storage unit including a plurality of ferroelectric elements, the nonvolatile storage unit configured to store the data held in the loop structure unit in a nonvolatile manner using hysteresis characteristics of the ferroelectric elements, and a circuit separation unit configured to electrically separate the loop structure unit and the nonvolatile storage unit. The ferroelectric elements of the nonvolatile storage unit are surrounded by a dummy element smaller in width than the ferroelectric elements.

摘要翻译： 数据保持装置包括：环路结构单元，被配置为使用以环形形式连接的多个逻辑门保存数据;非易失性存储单元，包括多个铁电元件;非易失性存储单元，被配置为存储保持在所述环路结构中的数据 使用铁电元件的滞后特性以非易失性方式单元，以及电路分离单元，其被配置为电气分离环路结构单元和非易失性存储单元。 非易失性存储单元的铁电元件被宽度小于铁电元件的虚拟元件围绕。

公开(公告)号：US20140087484A1

公开(公告)日：2014-03-27

申请号：US14010134

申请日：2013-08-26

申请人： Cypress Semiconductor Corporation

发明人： Shan Sun ,  Tom E. Davenport ,  John Cronin

IPC分类号： H01L27/115

CPC分类号： H01L27/11502 ,  H01L27/11504 ,  H01L28/55 ,  H01L28/90

摘要： A method for fabricating a non-volatile, ferroelectric random access memory (F-RAM) device is described. In one embodiment, the method includes forming an opening in an insulating layer over a surface of a substrate, and forming bottom electrode spacers proximal to sidewalls of the opening. Next, a ferroelectric dielectric layer is formed in the opening over the surface of the substrate and between the bottom electrode spacers, and a pair of top electrodes is formed within the opening comprising first and second side portions displaced laterally from respective ones of the bottom electrode spacers by the ferroelectric dielectric layer.

摘要翻译： 描述了制造非易失性铁电随机存取存储器（F-RAM）装置的方法。 在一个实施例中，该方法包括在衬底的表面上的绝缘层中形成开口，以及形成靠近开口侧壁的底部电极间隔件。 接下来，在基板的表面和底部电极间隔件之间的开口中形成铁电介质层，并且在该开口内形成一对顶部电极，该第一和第二侧面部分从底部电极 通过铁电介电层形成间隔物。

公开(公告)号：US20130037912A1

公开(公告)日：2013-02-14

申请号：US13569755

申请日：2012-08-08

申请人： Shan Sun ,  Thomas E. Davenport ,  John Cronin

发明人： Shan Sun ,  Thomas E. Davenport ,  John Cronin

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L27/11502 ,  H01L27/11504 ,  H01L28/55 ,  H01L28/90

摘要： Disclosed is a non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating the same in the form of a damascene self-aligned F-RAM device comprising a PZT capacitor built on the sidewalls of an oxide trench, while allowing for the simultaneous formation of two ferroelectric sidewall capacitors.

摘要翻译： 公开了一种非易失性铁电随机存取存储器（F-RAM）器件及其制造方法，其形式为镶嵌自对准的F-RAM器件，其包括内置于氧化物沟槽的侧壁上的PZT电容器， 同时允许同时形成两个铁电侧壁电容器。

公开(公告)号：US20130037872A1

公开(公告)日：2013-02-14

申请号：US13569785

申请日：2012-08-08

申请人： Shan SUN ,  Thomas E. DAVENPORT ,  John CRONIN

发明人： Shan SUN ,  Thomas E. DAVENPORT ,  John CRONIN

IPC分类号： H01L27/115 ,  H01L21/8239

CPC分类号： H01L43/02 ,  H01L27/11504 ,  H01L27/11507 ,  H01L27/228

摘要： Disclosed is a non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating a damascene self-aligned F-RAM that allows for the formation of a ferroelectric capacitor with separated PZT layers aligned with a preexisting, three dimensional (3-D) transistor structure.

摘要翻译： 公开了一种非易失性铁电随机存取存储器（F-RAM）装置和一种用于制造镶嵌自对准F-RAM的方法，其允许形成具有与预先存在的三维对准的分离的PZT层的铁电电容器 （3-D）晶体管结构。

公开(公告)号：US20120181607A1

公开(公告)日：2012-07-19

申请号：US13352194

申请日：2012-01-17

申请人： Ji-Do Ryu ,  Hee-Seog Jeon ,  Hyun-Khe Yoo ,  Yong-Suk Choi

发明人： Ji-Do Ryu ,  Hee-Seog Jeon ,  Hyun-Khe Yoo ,  Yong-Suk Choi

IPC分类号： H01L27/088

CPC分类号： H01L29/42328 ,  H01L21/28273 ,  H01L27/0207 ,  H01L27/11504 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L29/7883

摘要： A semiconductor device includes an active region in a substrate, first to third gate structures crossing the active region and sequentially arranged parallel to each other, a first doped region in the active region between the first and second gate structures and having a first horizontal width and a first depth, and a second doped region in the active region between the second and third gate structures and having a second horizontal width and a second depth. The second horizontal width is larger than the first horizontal width and the second depth is shallower than the first depth. A distance between the first and second gate structures adjacent to each other is smaller than that between the second and third gate structures adjacent to each other. Related fabrication methods are also described.

摘要翻译： 半导体器件包括在衬底中的有源区域，与有源区域交叉并顺序地彼此平行布置的第一至第三栅极结构，位于第一和第二栅极结构之间的有源区域中的第一掺杂区域，并且具有第一水平宽度和 第一深度和在第二和第三栅极结构之间的有源区域中的第二掺杂区域，并且具有第二水平宽度和第二深度。 第二水平宽度大于第一水平宽度，第二深度比第一深度浅。 彼此相邻的第一和第二栅极结构之间的距离小于彼此相邻的第二和第三栅极结构之间的距离。 还描述了相关的制造方法。

公开(公告)号：US08022504B2

公开(公告)日：2011-09-20

申请号：US12405565

申请日：2009-03-17

申请人： Hirotoshi Tachibana

发明人： Hirotoshi Tachibana

IPC分类号： H01L29/41 ,  H01L21/4763

CPC分类号： H01L28/55 ,  H01L27/11504 ,  H01L27/11507

摘要： A capacitor is formed over a semiconductor substrate. The capacitor includes a lower electrode, a capacitor dielectric film and an upper electrode in this order recited, and has an area S equal to or larger than 1000 μm2 and L/S equal to or larger than 0.4 μm−1, where S is an area of a capacitor region in which the lower and upper electrodes face each other across the dielectric film, and L is a total length of a circumference line of the capacitor region.

摘要翻译： 在半导体衬底上形成电容器。 电容器包括下列电极，电容器电介质膜和上部电极，其面积S等于或大于1000μm2，L / S等于或大于0.4μm-1，其中S为 下电极和上电极在电介质膜上彼此面对的电容器区域的面积，L是电容器区域的周长线的总长度。

公开(公告)号：US20110169135A1

公开(公告)日：2011-07-14

申请号：US13119070

申请日：2009-09-16

申请人： Yuichi Nakao

发明人： Yuichi Nakao

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L27/11507 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/32 ,  H01L21/76849 ,  H01L21/7687 ,  H01L27/11504 ,  H01L28/55 ,  H01L28/57 ,  H01L28/60 ,  H01L28/82

摘要： A semiconductor-storage-device manufacturing method of the present invention is a method for manufacturing a semiconductor storage device provided with a ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode, and the method includes a step of embedding a first metal plug and a second metal plug in an insulating layer; a step of forming a covering layer that covers at least the second metal plug while securing apart that comes into electric contact with the first metal plug; a step of forming a deposit structure by sequentially depositing a material for the lower electrode, a material for the ferroelectric film, and a material for the upper electrode after forming the covering layer; and a step of forming the ferroelectric capacitor by etching and removing other parts except a part of the deposit structure such that the part of the deposit structure remains on the first metal plug.

摘要翻译： 本发明的半导体存储元件的制造方法是具有下电极，强电介质膜和上电极的强电介质电容器的半导体存储元件的制造方法，其特征在于，包括： 金属插塞和绝缘层中的第二金属插塞; 形成覆盖层的步骤，所述覆盖层至少覆盖与所述第一金属插塞电接触的固定的所述第二金属插塞; 在形成覆盖层之后，依次沉积下电极材料，铁电薄膜材料和上电极材料，形成沉积结构的步骤; 以及通过蚀刻除去所述沉积结构的一部分以外的其它部分使得所述沉积结构的所述部分保留在所述第一金属插塞上而形成所述强电介质电容器的步骤。