公开(公告)号：US20140258795A1

公开(公告)日：2014-09-11

申请号：US14201559

申请日：2014-03-07

Applicant: Reiner SCHNIZLER ,  Paul Brooks

Inventor： Reiner SCHNIZLER ,  Paul Brooks

IPC: H04L1/24

CPC classification number: H04L1/241 ,  G01R31/2822 ,  G01R31/2839 ,  G06F7/58 ,  H04L1/20 ,  H04L1/244 ,  H04L25/064

Abstract: The invention relates to a method and device for testing a data link. A single-lane or multi-lane bit error tester that transmits one or more PRBS signals through the data link is augmented with a raw bit error buffer for storing bit error information for each detected error event and an error pattern analyzer. Most frequently occurring intra-lane bit error patterns, inter-lane word error patterns, and bit slip patterns are identified and their characteristics are analyzed so as to provide information indicative of root causes of the detected bit errors and bit slips.

Abstract translation: 本发明涉及一种用于测试数据链路的方法和设备。 通过数据链路传输一个或多个PRBS信号的单通道或多通道位错误测试器用用于存储针对每个检测到的错误事件的位错误信息的原始位错误缓冲器和错误模式分析器来增加。 识别最经常出现的车道内位错误模式，车道间字错误模式和位滑动模式，并分析其特性，以便提供指示检测到的位错误和位滑动的根本原因的信息。

公开(公告)号：US08817932B2

公开(公告)日：2014-08-26

申请号：US13967530

申请日：2013-08-15

Applicant: Rambus Inc.

Inventor： Andrew Ho ,  Vladimir Stojanovic ,  Bruno W. Garlepp ,  Fred F. Chen

IPC: H04L7/00 ,  H04L27/06

CPC classification number: H04B17/29 ,  G01R31/31711 ,  G06F11/08 ,  H04B17/21 ,  H04L1/20 ,  H04L1/241 ,  H04L1/242 ,  H04L7/033 ,  H04L7/043 ,  H04L7/10 ,  H04L25/03006 ,  H04L25/03057 ,  H04L25/03146 ,  H04L25/03949 ,  H04L27/01

Abstract: Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.

Abstract translation: 描述了数字接收机边缘测试的方法和电路。 这些方法和电路可以防止误差响应于错误接收的数据而崩溃，并且因此可以用在采用历史数据的接收机中以减少符号间干扰（ISI）。 一些实施例检测未知模式的输入数据流的接收错误，因此可以用于系统内边缘测试。 这样的系统可以适于在设备操作期间动态地改变系统参数，以保持足够的余量，尽管由于例如系统噪声环境的波动。 温度和电源电压变化。 还描述了绘制和解释由所公开的方法和电路产生的滤波和未滤波的误差数据的方法。 一些实施例可以过滤错误数据以促进模式特定的边缘测试。

公开(公告)号：US20130294490A1

公开(公告)日：2013-11-07

申请号：US13846491

申请日：2013-03-18

Applicant: Srinivasaraman Chandrasekaran ,  Kunal Desai

Inventor： Srinivasaraman Chandrasekaran ,  Kunal Desai

IPC: H04L7/00

CPC classification number: H04L1/205 ,  G01R31/31709 ,  G01R31/31726 ,  H04L1/241 ,  H04L1/242 ,  H04L7/0079 ,  H04L7/0083 ,  H04L7/10

Abstract: An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.

公开(公告)号：US08509295B1

公开(公告)日：2013-08-13

申请号：US12553656

申请日：2009-09-03

Applicant: Iddo Diukman

Inventor： Iddo Diukman

IPC: H04B3/46 ,  H04B17/00 ,  H04Q1/20

CPC classification number: H04B3/46 ,  H04B17/00 ,  H04B17/309 ,  H04B17/373 ,  H04B17/3912 ,  H04L1/203 ,  H04L1/241 ,  H04Q1/20

Abstract: Embodiments of the present disclosure provide a method for predicting bit errors in a communication channel, comprising generating a model representative of the communication channel, formulating enhanced noise at a first noise level that is higher than a second noise level, the second noise level corresponding to a level of noise that the communication channel experiences during a general operation of the communication channel, simulating an operation of the model by injecting the enhanced noise into the model, determining actual bit errors of the model when the model is simulated with the enhanced noise, and estimating a bit error rate (BER) when the model of the communication channel is operated with noise of the second level. Other embodiments are also described and claimed.

Abstract translation: 本公开的实施例提供了一种用于预测通信信道中的比特错误的方法，包括生成表示通信信道的模型，在高于第二噪声电平的第一噪声电平处制定增强的噪声，所述第二噪声电平对应于 通信信道在通信信道的一般操作期间经历的噪声水平，通过将增强的噪声注入模型来模拟模型的操作，当利用增强的噪声模拟模型时确定模型的实际位错误， 以及当通信信道的模型以第二级的噪声运行时，估计误码率（BER）。 还描述和要求保护其他实施例。

公开(公告)号：US20100020861A1

公开(公告)日：2010-01-28

申请号：US12558133

申请日：2009-09-11

Applicant: Brian S. Leibowitz ,  Bruno W. Garlepp

Inventor： Brian S. Leibowitz ,  Bruno W. Garlepp

IPC: H04L27/01

CPC classification number: H04L25/03057 ,  G01R31/31709 ,  G01R31/31711 ,  H04J11/0023 ,  H04L1/20 ,  H04L1/241 ,  H04L1/242 ,  H04L1/244 ,  H04L5/006 ,  H04L7/033 ,  H04L25/03146

Abstract: Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments allows feedback timing to be adjusted independent of the sample timing to measure the effects of some forms of phase misalignment and jitter.

Abstract translation: 描述了数字接收机边缘测试的方法和电路。 这些方法和电路可以防止误差响应于错误接收的数据而崩溃，并且因此可以用于采用历史数据的接收机来减少符号间干扰（ISI）。 一些实施例允许独立于采样定时来调整反馈定时以测量某些形式的相位未对准和抖动的影响。

公开(公告)号：US20060227912A1

公开(公告)日：2006-10-12

申请号：US11413584

申请日：2006-04-28

Applicant: Brian Leibowitz ,  Bruno Garlepp

Inventor： Brian Leibowitz ,  Bruno Garlepp

IPC: H04B1/10 ,  H04L7/00

CPC classification number: H04L25/03057 ,  G01R31/31709 ,  G01R31/31711 ,  H04J11/0023 ,  H04L1/20 ,  H04L1/241 ,  H04L1/242 ,  H04L1/244 ,  H04L5/006 ,  H04L7/033 ,  H04L25/03146

Abstract: Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments allows feedback timing to be adjusted independent of the sample timing to measure the effects of some forms of phase misalignment and jitter.

公开(公告)号：US06862701B2

公开(公告)日：2005-03-01

申请号：US09801031

申请日：2001-03-06

Applicant: Richard C. Walker ,  Patricia A. Thaler

Inventor： Richard C. Walker ,  Patricia A. Thaler

IPC: H04L12/26 ,  H04L1/24 ,  H04L29/14 ,  G01R31/28

CPC classification number: H04L1/244 ,  H04L1/203 ,  H04L1/241 ,  H04L1/242

Abstract: Self testing of a data communication system that includes a presettable scrambler and a complementary presettable descrambler is performed by presetting the presettable scrambler to a preset state. A seed payload field is scrambled using the presettable scrambler to generate fields of a test sequence. The fields of the test sequence are transmitted and corresponding received test sequence fields are received. The received test sequence fields are descrambled using the presettable descrambler to generate respective recovered test sequence fields. Differences between the recovered test sequence fields and the seed payload field are then detected as errors. In an embodiment, the seed payload field and the preset state of the presettable scrambler are chosen to generate a test sequence that imposes a known stress, such as a given run length, to the data communication system.

Abstract translation: 通过将预设的加扰器预设为预设状态来执行包括可预置的加扰器和互补预设解扰器的数据通信系统的自检。 使用可预设扰频器对种子有效载荷字段进行加扰，以生成测试序列的字段。 发送测试序列的字段并接收相应的接收到的测试序列字段。 接收的测试序列字段使用可预设的解扰器进行解扰，以产生相应的恢复的测试序列字段。 然后将恢复的测试序列字段和种子有效负载字段之间的差异检测为错误。 在一个实施例中，选择种子有效载荷字段和预设的加扰器的预设状态以产生将已知应力（例如给定的行程长度）施加到数据通信系统的测试序列。

公开(公告)号：US20040234014A1

公开(公告)日：2004-11-25

申请号：US10441461

申请日：2003-05-20

Inventor： Fred F. Chen

IPC: H04B015/00 ,  H04B001/10

CPC classification number: H04L1/20 ,  H04L1/241 ,  H04L1/242 ,  H04L1/244

Abstract: Described are methods and circuits for margin testing receivers equipped with Decision Feedback Equalization (DFE) or other forms of feedback that employ historical data to reduce intersymbol interference (ISI). In one example, a high-speed serial receiver with DFE injects the correct received data (i.e., the nullexpected datanull) into the feedback path irrespective of whether the receiver produces the correct output data. The margins are therefore maintained in the presence of receiver errors, allowing in-system margin tests to probe the margin boundaries without collapsing the margin limits. Some receivers include local expected-data sources that either store or generate expected data for margin tests. Other embodiments derive the expected data from test data applied to the receiver input terminals.

Abstract translation: 描述了配备有判决反馈均衡（DFE）或使用历史数据以减少符号间干扰（ISI）的其他形式的反馈的边缘测试接收机的方法和电路。 在一个示例中，具有DFE的高速串行接收机将正确的接收数据（即，“预期数据”）注入到反馈路径中，而不管接收机是否产生正确的输出数据。 因此，在存在接收器错误的情况下，维持利润率，允许在系统边际测试中探查边界边界，而不会使边界限制崩溃。 一些接收器包括存储或生成裕量测试的预期数据的本地预期数据源。 其他实施例从应用于接收机输入端的测试数据导出预期数据。

公开(公告)号：US06772378B1

公开(公告)日：2004-08-03

申请号：US09807029

申请日：2001-04-09

Applicant: Kenichi Ishihara ,  Kenichi Shiraishi ,  Soichi Shinjo ,  Akihiro Horii

Inventor： Kenichi Ishihara ,  Kenichi Shiraishi ,  Soichi Shinjo ,  Akihiro Horii

IPC: G06F1100

CPC classification number: H04L1/00 ,  H04L1/0003 ,  H04L1/241

Abstract: A dummy error addition circuit for adding a dummy error to an orthogonal modulation symbol data, wherein a value based on a specified bit error rate is loaded to count clock signals at a counter (11), a carrier of the counter (11) stores outputs from a PN data generator (21) in a shift register (22), outputs from a PN comparison circuit (3) when stored data agree with count values of the counter (11) are recognized as error pulses, a bit selector (40) randomly selects, on receiving error pulses and based on outputs from a PN data generator (41), bits to which to add errors in an orthogonal modulation data, e.g. a PSK modulation symbol data, at interval based on a bit error rate, and bits selected from the orthogonal modulation data are inverted in a bit inversion circuit (5) for outputting to thereby add errors.

Abstract translation: 一种用于向正交调制符号数据添加虚拟错误的虚拟错误添加电路，其中基于指定的误码率的值被加载以对计数器（11）计数时钟信号，计数器（11）的载波存储输出 当存储与计数器（11）的计数值一致的数据被识别为误差脉冲时，从PN比较电路（3）输出来自移位寄存器（22）中的PN数据发生器（21）的位选择器（40） 在接收到错误脉冲并基于PN数据生成器（41）的输出时，随机地选择在正交调制数据中添加错误的位，例如 基于比特误码率的间隔的PSK调制符号数据和从正交调制数据中选择的比特在比特反相电路（5）中反转，从而输出错误。

公开(公告)号：US5870428A

公开(公告)日：1999-02-09

申请号：US566755

申请日：1995-12-04

Applicant: David E. Miller ,  Robert A. Barrett ,  David E. Wilder

Inventor： David E. Miller ,  Robert A. Barrett ,  David E. Wilder

IPC: H04L1/24 ,  H04B1/38 ,  H04L5/16

CPC classification number: H04L1/243 ,  H04L1/241

Abstract: An adaptive digital data unit (600) initiates and successfully completes a remote loop back test. The adaptive digital data unit (600) has a controller (610), a local transmitter (620), a local receiver (640) a timer (622) and a detector (634). When a remote adaptive digital data unit (600) transmits a first data sequence and a second data sequence, the local adaptive digital data unit (600) receives the second data sequence from the remote digital data unit and determines if the second data sequence matches one of two predetermined data sequences. If so, a test successful flag is generated.

Abstract translation: 自适应数字数据单元（600）启动并成功完成远程环回测试。 自适应数字数据单元（600）具有控制器（610），本地发射机（620），本地接收机（640）定时器（622）和检测器（634）。 当远程自适应数字数据单元（600）发送第一数据序列和第二数据序列时，本地自适应数字数据单元（600）从远程数字数据单元接收第二数据序列，并确定第二数据序列是否匹配一个 的两个预定数据序列。 如果是，则生成测试成功标志。