公开(公告)号：US5790602A

公开(公告)日：1998-08-04

申请号：US573421

申请日：1995-12-15

申请人： Donald R. Stephens

发明人： Donald R. Stephens

IPC分类号： H03J7/02 ,  H04L7/04 ,  H04L27/227 ,  H04L27/233 ,  H04L27/22 ,  H04L7/00

CPC分类号： H04L27/2272 ,  H03J7/02 ,  H04L27/233 ,  H04L7/041

摘要： A receiver carrier synchronization apparatus and method for carrier synchronization with a received signal having a known data pattern preamble uses a "punctured" preamble for making carrier synchronization estimates thereby reducing the number of receivers required. The known data pattern preamble of the received signal is processed with a local reference signal and a differentiated replica of the known data pattern preamble to generate an error signal. The error signal is selectively sampled in the time domain in accordance with a puncture scheme, and the sampled error signal is used to generate the local reference signal in a closed loop. The received signal is processed with the local reference signal and a replica of the known data pattern preamble to generate a synchronization estimate signal.

公开(公告)号：US5544200A

公开(公告)日：1996-08-06

申请号：US351797

申请日：1994-12-08

申请人： Song H. An

发明人： Song H. An

IPC分类号： H04L7/033 ,  H04L27/227 ,  H04L27/06

CPC分类号： H04L27/2272 ,  H04L7/0334

摘要： A signal acquisition system rapidly acquires carrier phase and symbol timing of a received PSK-modulated communication signal having a 110-symbol pattern through joint estimation of carrier-phase adjustment and symbol-timing adjustment by processing a common set of sampled data. A reference signal at a local oscillator frequency is mixed with a received communication signal to provide the communication signal at an intermediate frequency. The intermediate-frequency communication signal is converted into a digital communication signal, which is formatted into in-phase (I) and quadrature-phase (Q) components. A sampling circuit samples the I components at twice a predetermined symbol rate to provide a first series of I-component samples at the predetermined symbol rate and a second series of I-component samples that are intermediate to the first series of I-component samples and at the predetermined symbol rate, and for sampling the Q components at twice the predetermined symbol rate to provide a first series of Q-component samples at the predetermined symbol rate and a second series of Q-component samples that are intermediate to the first series of Q-component samples and at the predetermined symbol rate. A processor processes the samples to estimate a phase-adjustment value and a symbol-timing-adjustment value. The phase of the reference signal is adjusted in accordance with the phase-adjustment value and the timing of the sampling is adjusted in accordance with the symbol-timing-adjustment value.

摘要翻译： 信号采集系统通过共同估计载波相位调整和符号定时调整，通过处理一组共同的采样数据，快速获取具有110符号模式的接收的PSK调制通信信号的载波相位和符号定时。 以本地振荡器频率的参考信号与接收的通信信号混合，以提供中频的通信信号。 中频通信信号被转换为数字通信信号，其被格式化为同相（I）和正交相（Q）分量。 采样电路以预定符号率两倍对I分量进行采样，以提供以预定符号速率的第一系列I分量样本和位于第一系列I分量采样之间的第二系列I分量采样， 以预定符号率进行采样，并且以两倍于预定符号速率对Q个分量进行采样，以提供预定符号速率的第一系列Q分量样本和第二系列Q分量样本， Q分量样本并以预定的符号率。 处理器处理采样以估计相位调整值和符号定时调整值。 根据相位调整值调整参考信号的相位，并根据符号定时调整值调整采样的定时。

公开(公告)号：US5090025A

公开(公告)日：1992-02-18

申请号：US558197

申请日：1990-07-24

申请人： Alan C. Marshall ,  Stuart P. MacEachern ,  Howard C. Salwen

发明人： Alan C. Marshall ,  Stuart P. MacEachern ,  Howard C. Salwen

IPC分类号： H04L7/00 ,  H04L7/033 ,  H04L12/42 ,  H04L25/60 ,  H04L27/227

CPC分类号： H04L27/2272 ,  H04L12/422 ,  H04L7/033

摘要： An improved local area network node of the type described in ANSI/IEEE Standard 802.5, including a receiver-demodulator having an input connectable to the ring and having a received data output and a received clock output, an elasticity buffer connected to the received data output, a modulator for modulating the output of the buffer in accordance with a signal at a clocking input of the modulator, and a phase-locked loop interposed between the received clock output of the demodulator and the clocking input of the modulator, the loop including a voltage-controlled oscillator, a phase detector and a filter connected for providing a control-voltage to the oscillator.

摘要翻译： ANSI / IEEE标准802.5中所述类型的改进的局域网节点，包括接收机解调器，其具有可连接到环的输入端并具有接收的数据输出和接收到的时钟输出;连接到接收的数据输出的弹性缓冲器 调制器，用于根据调制器的时钟输入处的信号调制缓冲器的输出，以及插入在解调器的接收时钟输出端和调制器的时钟输入端之间的锁相环，该环路包括一个 压控振荡器，相位检测器和连接用于向振荡器提供控制电压的滤波器。

公开(公告)号：US4742532A

公开(公告)日：1988-05-03

申请号：US861049

申请日：1986-05-08

申请人： Harold R. Walker

发明人： Harold R. Walker

IPC分类号： H04L27/20 ,  H04L27/227 ,  H04L27/18

CPC分类号： H04L27/2272 ,  H04L27/2035

摘要： There is disclosed a high speed data transmission system for transmitting a binary data signal over a communications path. The binary data signal is clocked at a given period. The system comprises encoded means responsive to a binary NRZ input data signal to provide at an output an encoded digital signal having time periods greater than multiples of the clock period, whereby the encoded signal occupies a lesser effective bandwidth than the NRZ signal would occupy. There are balanced modulator means having an input responsive to the encoded signal and another input adapted to receive a carrier frequency to provide at an output a double sideband suppressed carrier signal. Coupled to the output of the balanced modulator are narrow bandwidth filtering means including first low pass and second high pass parallel filter paths each having a common input terminal coupled to the output of the modulator. The ouputs of the low and high pass filters are symmetrically combined to provide a narrow single sideband signal for transmission characterized in that transitions between binary levels in said encoded signal are manifested by distinct phase changes in said single sideband signal.

摘要翻译： 公开了一种用于通过通信路径发送二进制数据信号的高速数据传输系统。 二进制数据信号在给定的时间段进行计时。 该系统包括响应于二进制NRZ输入数据信号的编码装置，以在输出端提供具有大于时钟周期的倍数的时间周期的编码数字信号，由此编码信号占用比NRZ信号将占用的有效带宽更小。 存在平衡调制器装置，其具有响应于编码信号的输入和适于接收载波频率的另一输入，以在输出处提供双边带抑制载波信号。 耦合到平衡调制器的输出是窄带宽滤波装置，包括第一低通和第二高通并行滤波器路径，每个具有耦合到调制器的输出的公共输入端。 低通滤波器和高通滤波器的输出被对称组合以提供用于传输的窄单边带信号，其特征在于，所述编码信号中的二进制电平之间的转换由所述单边带信号中的不同相位变化表现出来。

公开(公告)号：US4642573A

公开(公告)日：1987-02-10

申请号：US783521

申请日：1985-10-03

申请人： Tsutomu Noda ,  Keiro Shinkawa ,  Nobutaka Amada

发明人： Tsutomu Noda ,  Keiro Shinkawa ,  Nobutaka Amada

IPC分类号： H03D1/24 ,  H03D3/24 ,  H03D7/16 ,  H03L7/087 ,  H04L27/227 ,  H03D3/02 ,  H04L27/22

CPC分类号： H04L27/2272 ,  H03D3/242 ,  H03D3/245 ,  H03L7/087 ,  H03D2200/0031 ,  H03D7/161

摘要： A phase locked loop circuit for use in a heterodyne receiver for stably demodulating a carrier-suppressed double-sideband signal such as a 2-phase or 4-phase PSK signal. The phase locked loop circuit comprises a reference oscillator oscillating at a frequency corresponding to an intermediate frequency, and the frequency difference between the reference frequency and the input frequency is detected by a Costas loop, a signal indicative of the frequency difference being fed back to a local oscillator through a loop filter thereby stabilizing the intermediate frequency.

摘要翻译： 一种用于外差接收机的锁相环电路，用于稳定解调诸如2相或4相PSK信号的载波抑制双边带信号。 锁相环电路包括以对应于中频的频率振荡的参考振荡器，并且通过科斯塔斯回路检测参考频率与输入频率之间的频率差，表示频差的信号被反馈到 本地振荡器通过环路滤波器，从而稳定中频。

公开(公告)号：US4627079A

公开(公告)日：1986-12-02

申请号：US549536

申请日：1983-11-07

申请人： Urban A. von der Embse

发明人： Urban A. von der Embse

IPC分类号： H04L25/49 ,  H04L27/227 ,  H04B1/16 ,  H04L27/00

CPC分类号： H04L25/4904 ,  H04L27/2272

摘要： A receiver is disclosed for acquiring and tracking a data signal in a highly stressed environment. The receiver comprises first and second I.F. sections, a mixer for translation from the first I.F. frequency to the second I.F. frequency, a 2 KHz bandpass filter at the second I.F. frequency, signal translator for synchronous translation of the signal at the second I.F. frequency to baseband, a digitizer for complex sampling operation on the baseband signal, a microprocessor for processing the digital samples, and a numerically controlled oscillator coupled to the mixer and controlled by the microprocessor. The microprocessor formulates matched digital discrete Fourier Transform filters which drive frequency, phase and symbol lock loops at the symbol rate. Each of the loop filters is formed by symbol-rate recursive, first-order equations. A novel mode control system is employed to implement an orderly transition through the receiver modes, comprising (i) out-of-band noise estimation, (ii) coarse frequency and time acquisition of the data signal employing a sequential probability ratio test and a handover process, (iii) frequency and symbol synchronization with the data signal, (iv) phase and symbol synchronization with the data signal, and (v) feedback loop lock confirmation. After loss of lock, the mode controller transfers the receiver operations back to the appropriate restart operation.

摘要翻译： 公开了用于在高度应力环境中获取和跟踪数据信号的接收器。 接收机包括第一和第二I.F. 部分，从第一个I.F.翻译的搅拌机 频率到第二个I.F. 频率为2KHz带通滤波器。 频率信号转换器，用于在第二个IF处的信号同步转换。 频率到基带，用于对基带信号进行复杂采样操作的数字转换器，用于处理数字样本的微处理器，以及耦合到混频器并由微处理器控制的数控振荡器。 微处理器制定匹配的数字离散傅里叶变换滤波器，以符号速率驱动频率，相位和符号锁定环路。 每个环路滤波器由符号速率递归的一阶方程组成。 采用新颖的模式控制系统来实现通过接收机模式的有序转换，包括（i）带外噪声估计，（ii）使用连续概率比测试和切换的数据信号的粗略频率和时间获取 过程，（iii）与数据信号的频率和符号同步，（iv）与数据信号的相位和符号同步，以及（v）反馈回路锁定确认。 锁定失败后，模式控制器将接收机操作重新传送回适当的重启操作。

公开(公告)号：US4389616A

公开(公告)日：1983-06-21

申请号：US217519

申请日：1980-12-15

申请人： Heinz Gockler ,  Hagen Hofmeister

发明人： Heinz Gockler ,  Hagen Hofmeister

IPC分类号： H04L27/227 ,  H04L27/22

CPC分类号： H04L27/2272

摘要： A method for digitally regulating the residual carrier phase error in receivers of digital data transmission systems. A comparator compares the sampled data signal or value of the carrier demodulated input signal to the receiver with the estimated value for each associated sampling time or moment as provided by a decider, to determine the deviation dk which is a measure for the phase difference between the sampled value and the associated estimated value. This deviation dk is filtered in a digital loop filter, including a proportional branch and an integration branch, and a regulating value for the demodulated input signal is obtained from a subsequently connected accumulator. A non-linear limitation on the deviation dk is included in the integration branch of the digital loop filter.

摘要翻译： 一种用于数字调节数字数据传输系统接收机中的载波相位误差的方法。 比较器将采样的数据信号或载波解调输入信号的值与接收机进行比较，其中每个相关采样时间或时刻的估计值由判定器提供，以确定偏差dk，该偏差是对 采样值和相关估计值。 该偏差dk在包括比例分支和积分分支的数字环路滤波器中被滤波，并且从随后连接的累加器获得解调输入信号的调节值。 偏差dk的非线性限制包含在数字环路滤波器的积分分支中。

公开(公告)号：US4339725A

公开(公告)日：1982-07-13

申请号：US133744

申请日：1980-03-25

申请人： Osamu Ichiyoshi

发明人： Osamu Ichiyoshi

IPC分类号： H04L27/227 ,  H03D3/18 ,  H04L27/22

CPC分类号： H04L27/2272

摘要： An N-phase PSK demodulator is disclosed wherein all circuits therein operate in a frequency band equal to or below the carrier band. The locally reproduced carrier is generated by a phase locked loop in combination with a frequency converter means and a divide-by-two frequency divider. The frequency converter means consists of n identical frequency converter circuits connected in series, where 2.sup.n =N. For a 2-phase PSK demodulator where n=1, the 2-phase PSK modulated wave is applied as a first input and the reproduced carrier divided by two is applied as a second input to the frequency converter circuit. A mixer and filter provide as an output the difference frequency between the first and second inputs. The latter output is multiplied by two and applied as the input to the phase locked loop. Where n>1, the first input of each frequency converter circuit except the first is the output from the preceeding circuit, and the output from the last frequency converter circuit is the input to the phase locked loop.

摘要翻译： 公开了一种N相PSK解调器，其中其中所有电路在等于或低于载波频带的频带内工作。 本地再现的载波由与频率转换器装置和分频二分频器组合的锁相环产生。 变频器装置由串联连接的n个相同的变频器电路组成，其中2n = N。 对于n = 1的2相PSK解调器，将2相PSK调制波作为第一输入，并将再生载波除以2作为第二输入施加到变频器电路。 混频器和滤波器作为输出提供第一和第二输入之间的差频。 后一个输出乘以2并作为输入施加到锁相环。 其中n> 1，除了第一个之外的每个变频器电路的第一个输入是前一个电路的输出，最后一个变频器电路的输出是锁相环的输入。

公开(公告)号：US4313219A

公开(公告)日：1982-01-26

申请号：US129392

申请日：1980-03-11

申请人： Egmont Gabler ,  Uwe Lehmann

发明人： Egmont Gabler ,  Uwe Lehmann

IPC分类号： H04B1/26 ,  H03J7/04 ,  H03L7/06 ,  H04L27/227 ,  H03D3/02

CPC分类号： H04L27/2272 ,  H03J7/04 ,  H03L7/06

摘要： A receiver for high frequency electromagnetic oscillations, having frequency readjustment with a voltage-control oscillator, includes a phase control loop for regaining the carrier in the signal path of the receiver. The phase control loop comprises a device for recovering the carrier, a phase-locked loop oscillator and phase detector which receives the output signal of the carrier recovery device and the oscillations of the phase-locked loop oscillator as a reference, and a demodulator which receives the modulated input signal and the output of the phase-locked loop oscillator.

摘要翻译： 用于具有电压控制振荡器的频率重新调整的用于高频电磁振荡的接收器包括用于在接收机的信号路径中重新获得载波的相位控制环路。 相位控制回路包括用于恢复载波的装置，接收载波恢复装置的输出信号和锁相环振荡器的振荡作为参考的锁相环振荡器和相位检测器，以及接收 调制输入信号和锁相环振荡器的输出。

公开(公告)号：US4297650A

公开(公告)日：1981-10-27

申请号：US108249

申请日：1979-12-27

申请人： Saburo Shinmyo

发明人： Saburo Shinmyo

IPC分类号： H03L7/087 ,  H03L7/10 ,  H04L27/227

CPC分类号： H01L21/324 ,  H03L7/087 ,  H03L7/10 ,  H04L27/2272 ,  H03L2207/14 ,  Y10S331/02

摘要： A carrier recovery apparatus for phase modulated waves including phase-locked loops is operable to prevent false locks. The apparatus includes a clock recovery circuit which generates a signal in response to a modulated carrier, a first phase comparator responsive to the modulated carrier and the output of a VCO, a second phase comparator responsive to the first phase comparator and the clock signal, and a control device for superimposing the low frequency component of the output of the second phase comparator on the output of the first phase comparator or a loop filter which controls the VCO.

摘要翻译： 包括锁相环的相位调制波的载波恢复装置可操作以防止假锁。 该装置包括响应于调制载波产生信号的时钟恢复电路，响应调制载波和VCO输出的第一相位比较器，响应于第一相位比较器和时钟信号的第二相位比较器，以及 用于将第二相位比较器的输出的低频分量叠加在第一相位比较器的输出端上的控制装置或控制VCO的环路滤波器。