公开(公告)号：US11049835B2

公开(公告)日：2021-06-29

申请号：US16508739

申请日：2019-07-11

申请人： Murata Manufacturing Co., Ltd.

发明人： Tsunekazu Saimei ,  Takeshi Suzuki ,  Masashi Yamaura

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L23/29 ,  H01L21/52 ,  H01L21/56 ,  H01L23/13 ,  H01L23/12 ,  H01L23/31 ,  H01L23/488

摘要： A semiconductor module that restrains the occurrence of detachment and an operation failure. The semiconductor module includes a PCB base, a conductive die pad provided on the PCB base, a semiconductor die provided on the conductive die pad, and a conductive die bonding agent that electrically connects the conductive die pad and the semiconductor die. The semiconductor module further includes a wire bonding pad provided on the PCB base, a wire that electrically connects the wire bonding pad and the semiconductor die, and a sealing resin that seals the conductive die pad, the semiconductor die, the conductive die bonding agent, the wire bonding pad, and the wire. In a planar view, the area of the conductive die pad is 5.0 mm2 or less.

公开(公告)号：US20210183747A1

公开(公告)日：2021-06-17

申请号：US17190261

申请日：2021-03-02

申请人： PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

发明人： Hidekazu NAKAMURA ,  Manabu YANAGIHARA ,  Tomohiko NAKAMURA ,  Yusuke KATAGIRI ,  Katsumi OTANI ,  Takeshi KAWABATA

IPC分类号： H01L23/495 ,  H01L29/20 ,  H01L23/00 ,  H01L25/07 ,  H01L25/18 ,  H01L21/52 ,  H01L23/48

摘要： A semiconductor device that is a surface mount-type device includes a nitride semiconductor chip including a silicon substrate having a first thermal expansion coefficient and an InxGayAl1-x-yN layer in contact with a surface of the silicon substrate, where 0≤x≤1, 0≤y≤1, 0≤x+y ≤1; and a die pad including
Cu and having a second thermal expansion coefficient that is greater than the first thermal expansion coefficient. A thickness of the nitride semiconductor chip is at least 0.2 mm, length L of the nitride semiconductor chip is at least 3.12 mm, and thickness tm of the die pad and length L of the nitride semiconductor chip satisfy tm ≥2.00×10−3×L2+0.173, tm being a thickness in mm and L being a length in mm.

公开(公告)号：US11037844B2

公开(公告)日：2021-06-15

申请号：US15858418

申请日：2017-12-29

申请人： Mitsubishi Electric Corporation

发明人： Satoshi Kondo ,  Yusuke Kaji

IPC分类号： H01L23/04 ,  H01L23/24 ,  H01L21/54 ,  H01L23/22 ,  H01L23/053 ,  H01L23/047 ,  H01L21/52 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H02M7/00 ,  H01L23/367 ,  H02M7/5387

摘要： A power semiconductor device includes a casing, a first insulating circuit board, a second insulating circuit board, and a sealing material. The first insulating circuit board is disposed to be surrounded by the casing. The second insulating circuit board is surrounded by the casing and spaced from the first insulating circuit board so as to sandwich a semiconductor element between the first insulating circuit board and the second insulating circuit board. The sealing material fills a region surrounded by the casing. The first or second insulating circuit board is provided with a hole extending from one main surface to the other main surface opposite to one main surface. From at least a portion of an inner wall surface of the casing a protrusion extending to a region overlapping the first or second insulating circuit board in a plan view extends toward the region surrounded by the casing.

公开(公告)号：US20210175162A1

公开(公告)日：2021-06-10

申请号：US17180835

申请日：2021-02-21

申请人： BroadPak Corporation

发明人： Farhang YAZDANI

IPC分类号： H01L23/498 ,  H01L25/00 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31 ,  H01L21/52 ,  H01L23/473 ,  H01L23/66 ,  H01L23/04 ,  H01L25/065 ,  H01L25/18 ,  H01L25/10

摘要： A system comprising a plurality of electronic components, wherein said plurality of electronic components including a first component and a second component, and said first component is a security component configured to generate and/or store security key(s); a substrate; one or more standoff substrate(s) comprising of cavity(3ies), wherein said one or more standoff substrate(s) is/are coupled to said substrate, said one or more standoff substrate(s) completely encircles said substrate, said security component is disposed inside said cavity(ies), said security component is coupled to said substrate, said security component is obfuscated by said substrate and said one or more standoff substrate(s), and said security component and said second component are configured to communicate security key(s) for performing device identification, authentication, encryption, and/or device integrity verification.

公开(公告)号：US11018072B2

公开(公告)日：2021-05-25

申请号：US16520058

申请日：2019-07-23

申请人： Infineon Technologies AG

发明人： Juergen Hoegerl ,  Ordwin Haase ,  Tobias Kist

IPC分类号： H01L21/00 ,  H01L23/34 ,  H01L23/367 ,  H01L23/492 ,  H01L23/373 ,  H01L23/495 ,  H01L25/16 ,  H01L23/31 ,  H01L29/16 ,  H01L21/56 ,  H01L21/52 ,  H01L23/433

摘要： A semiconductor package includes an upper electrically conductive element having a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer arranged between the electrically conductive layers, a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer, a power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer, and a second electrically conductive spacer arranged between the upper electrically conductive element and the chip. A first carrier region of the upper electrically conductive layer is configured to apply a positive supply voltage. A second carrier region alongside the first carrier region is configured as a phase. A first region of the upper electrically conductive element is configured to apply a negative supply voltage, and at least partly overlaps the first carrier region.

公开(公告)号：US20210125974A1

公开(公告)日：2021-04-29

申请号：US16664652

申请日：2019-10-25

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Tsung-Yueh TSAI ,  Meng-Jen WANG ,  Yu-Fang TSAI ,  Meng-Jung CHUANG

IPC分类号： H01L25/16 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/52

摘要： An optical device package comprises a carrier having a first surface and a second surface recessed with respect to the first surface and a lid disposed on the second surface of the carrier.

公开(公告)号：US10971455B2

公开(公告)日：2021-04-06

申请号：US16400264

申请日：2019-05-01

申请人： QUALCOMM Incorporated

发明人： Aniket Patil ,  Kuiwon Kang ,  Zhijie Wang ,  Ming Yi

IPC分类号： H01L23/552 ,  H01L23/04 ,  H01L23/49 ,  H01L23/498 ,  H01L21/52 ,  H01L23/556

摘要： Certain aspects of the present disclosure provide an integrated circuit (IC) package and techniques for fabricating the IC package. The IC package generally includes a substrate, an IC disposed above the substrate, and a shielding layer coupled to a layer of the substrate, wherein the shielding layer is disposed above the substrate adjacent to the IC, and below an upper surface of the IC.

公开(公告)号：US20210066164A1

公开(公告)日：2021-03-04

申请号：US16798431

申请日：2020-02-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chung-Jung Wu ,  Chih-Hang Tung ,  Tung-Liang Shao ,  Sheng-Tsung Hsiao ,  Jen-Yu Wang

IPC分类号： H01L23/46 ,  H01L23/40 ,  H01L23/498 ,  H01L21/52

摘要： A semiconductor device includes a package and a cooling cover. The package includes a first die having an active surface and a rear surface opposite to the active surface. The rear surface has a cooling region and a peripheral region enclosing the cooling region. The first die includes micro-trenches located in the cooling region of the rear surface. The cooling cover is stacked on the first die. The cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling region and communicated with the micro-trenches.

公开(公告)号：US10892231B2

公开(公告)日：2021-01-12

申请号：US16667376

申请日：2019-10-29

申请人： General Electric Company

发明人： Christopher James Kapusta ,  Raymond Albert Fillion ,  Risto Ilkka Sakari Tuominen ,  Kaustubh Ravindra Nagarkar

IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L21/52 ,  H01L23/31 ,  H01L23/552 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

摘要： An electronics package includes a support substrate, an electrical component having a first surface coupled to a first surface of the support substrate, and an insulating structure coupled to the first surface of the support substrate and sidewalls of the electrical component. The insulating structure has a sloped outer surface. A conductive layer encapsulates the electrical component and the sloped outer surface of the insulating structure. A first wiring layer is formed on a second surface of the support substrate. The first wiring layer is coupled to the conductive layer through at least one via in the support substrate.

公开(公告)号：US10825747B2

公开(公告)日：2020-11-03

申请号：US15710098

申请日：2017-09-20

申请人： NXP USA, INC.

发明人： Li Li ,  Jaynal A. Molla ,  Lakshminarayan Viswanathan

IPC分类号： H01L23/34 ,  H01L23/047 ,  H01L21/52 ,  H01L23/373 ,  H01L21/56 ,  H01L21/60 ,  H01L21/50 ,  H01L23/00 ,  H01L23/433 ,  H01L23/31 ,  H01L21/603

摘要： A method of manufacturing a packaged semiconductor device includes forming an assembly by placing a semiconductor die over a substrate with a die attach material between the semiconductor die and the substrate. A conformal structure which includes a pressure transmissive material contacts at least a portion of a top surface of the semiconductor die. A pressure is applied to the conformal structure and in turn, the pressure is transmitted to the top surface of the semiconductor die by the pressure transmissive material. While the pressure is applied, concurrently encapsulating the assembly with a molding compound and exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter.