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394 条记录 (耗时 0.016 秒)

    Multi-nary and logic device
    61.
    发明授权
    Multi-nary and logic device 失效
    多功能和逻辑器件

    公开(公告)号：US5463572A

    公开(公告)日：1995-10-31

    申请号：US357246

    申请日：1994-12-13

    申请人： Jin-Up Kim ,  Sun-Young Kim

    发明人： Jin-Up Kim ,  Sun-Young Kim

    IPC分类号： G06F7/50 ,  G06F7/44 ,  G06F7/49 ,  G06F7/501 ,  H03K19/20 ,  G06F7/00

    CPC分类号： G06F7/49

    摘要： An AND logic operation rule capable of carrying out an AND logic operation between binary digits and an AND logic operation between multi-nary digits is defined and an AND logic device utilizing the AND logic operation is disclosed. The AND logic operator having three multi-nary logic inputs consists of two multi-nary AND logic operators having two inputs, respectively. The multi-nary AND logic operator carries out the function of the prior binary AND logic operation and the function of the binary-multi-nary AND logic operation.

    摘要翻译： 定义能够执行二进制数位之间的AND逻辑运算和多数位之间的AND逻辑运算的AND逻辑运算规则，并且公开了利用AND逻辑运算的AND逻辑器件。 具有三个多逻辑逻辑输入的AND逻辑运算器分别由具有两个输入的两个多参数AND逻辑运算符组成。 多逻辑AND逻辑运算符执行先前的二进制AND逻辑运算和二进制多逻辑和逻辑运算的功能。

    Scaler circuit
    62.
    发明授权
    Scaler circuit 失效
    整流电路

    公开(公告)号：US5457417A

    公开(公告)日：1995-10-10

    申请号：US191495

    申请日：1994-02-04

    申请人： Shou Guoliang ,  Weikang Yang ,  Sunao Takatori ,  Makoto Yamamoto

    发明人： Shou Guoliang ,  Weikang Yang ,  Sunao Takatori ,  Makoto Yamamoto

    IPC分类号： G06G7/14 ,  G06G7/12 ,  G06J1/00 ,  H03F3/34 ,  H03G1/00 ,  H03G3/00 ,  H03G3/10 ,  G06F7/44

    CPC分类号： G06G7/12 ,  G06J1/00 ,  H03G1/0094

    摘要： A scalar circuit includes serially connected inverters connected to one another via a plurality of connecting lines. A plurality of input lines are provided to the input of a first inverter in the serially connected inverters. A plurality of feedback lines are provided between the input and output of each inverter. A capacitance and a switch is provided in each connecting line, input line and feedback line. The switch connects a terminal of the capacitance to ground while simultaneously disconnecting the ends of that line from one another. The switches are cooperatively actuated so that the effective composite capacitance in the feedback lines and the connecting lines are substantially equal. In addition, the composite capacitance of in the input lines and the connecting lines are substantially equal.

    摘要翻译： 标量电路包括通过多条连接线彼此连接的串联逆变器。 多个输入线被提供给串联逆变器中的第一反相器的输入端。 在每个逆变器的输入和输出之间提供多条反馈线。 每个连接线，输入线和反馈线都提供电容和开关。 开关将电容的端子连接到地，同时断开该线的端部。 这些开关被协同地致动，使得反馈线和连接线中的有效复合电容基本相等。 此外，输入线和连接线中的复合电容基本相等。

    Booth's conversion circuit
    63.
    发明授权
    Booth's conversion circuit 失效
    展位的转换电路

    公开(公告)号：US4798980A

    公开(公告)日：1989-01-17

    申请号：US49141

    申请日：1987-05-13

    申请人： Hisashi Sugiyama ,  Yasuhiro Sugimoto ,  Yukio Kamatani

    发明人： Hisashi Sugiyama ,  Yasuhiro Sugimoto ,  Yukio Kamatani

    IPC分类号： G06F7/53 ,  G06F7/44 ,  G06F7/52 ,  G06F7/533 ,  H03K19/21 ,  H03K19/017 ,  H03K19/094

    CPC分类号： G06F7/5332

    摘要： A Booth's algorithm conversion circuit having first and second switches controlled by input signals QX and Q2X and receiving as input, signals X.sub.i of a logic level positioned in the i digit order of a multiplicand X and signal X.sub.i-1 of a logic level positioned in the i-1 digit order of multiplicand X. The outputs of the first and second switches are tied together and to ground via first and second transitors controlled by signals QX and Q2X, the first and second transistors conducting in an inverse relationship to the first and second switch circuits. The common output of the first and second switch circuits is input to an exclusive OR circuit which receives an additional logic 1 or logic 0 input signal to produce the Booth's converted output. The resulting number of circuit elements and gates provides a simplified, high speed and small circuit for producing the Booth's conversion.

    摘要翻译： 一种展位的算法转换电路，具有由输入信号QX和Q2X控制的第一和第二开关，并且接收位于被乘数X的i数位顺序的逻辑电平的信号Xi和位于该位置的逻辑电平的信号Xi-1 被乘数X的i-1位数。第一和第二开关的输出通过由信号QX和Q2X控制的第一和第二转换器连接在一起并接地，第一和第二晶体管与第一和第二开关反向关系 开关电路。 第一和第二开关电路的公共输出被输入到异或电路，该异或电路接收额外的逻辑1或逻辑0输入信号以产生布斯的转换输出。 所产生的电路元件和门的数量提供了简化的高速和小电路，用于生产Booth的转换。

    Parallel processor having central processor memory extension
    64.
    发明授权
    Parallel processor having central processor memory extension 失效
    具有中央处理器内存扩展的并行处理器

    公开(公告)号：US4310879A

    公开(公告)日：1982-01-12

    申请号：US18476

    申请日：1979-03-08

    申请人： Arun K. Pandeya

    发明人： Arun K. Pandeya

    IPC分类号： G06F7/50 ,  G06F7/52 ,  G06F7/57 ,  G06F15/80 ,  G06F7/42 ,  G06F7/44 ,  G06F9/28 ,  G06F13/00

    CPC分类号： G06F7/5324 ,  G06F15/8007 ,  G06F7/483 ,  G06F7/485 ,  G06F7/4876 ,  G06F7/509 ,  G06F2207/3896 ,  G06F7/4991 ,  G06F7/49921 ,  G06F7/49936 ,  G06F7/49942

    摘要： An array processor which is an integral part of a central processing unit (CPU) has a local memory which is part of main memory address space. Furthermore, the array procesor has its own port into the local memory, leaving a system bus free while the array processor is working. The array processor is controlled so that data can be transferred between the main memory and the local memory either before, during, or after operation of data manipulation hardware which is part of the array processor. This data manipulation hardware utilizes a fast multiplier, and fast add, subtract, & compare circuitry. The array processor is controlled by a 76 bit microcode extension to one sector of a number of sectors of a control store in the CPU. The microcode extension can be overriden by interrupt and other control signals generated by the CPU.

    摘要翻译： 作为中央处理单元（CPU）的组成部分的阵列处理器具有作为主存储器地址空间的一部分的本地存储器。 此外，阵列处理器有自己的端口到本地存储器中，在阵列处理器正在工作时，使系统总线空闲。 控制阵列处理器，以便数据可以在作为阵列处理器的一部分的数据操作硬件的操作之前，期间或之后在主存储器和本地存储器之间传送。 该数据处理硬件使用快速乘法器，并且快速加，减和比较电路。 阵列处理器由CPU中控制存储器的多个扇区的一个扇区的76位微代码扩展控制。 微代码扩展可以通过CPU产生的中断和其他控制信号来覆盖。

    Decimal data-handling equipment
    65.
    发明授权
    Decimal data-handling equipment 失效
    十进制数据处理设备

    公开(公告)号：US3594561A

    公开(公告)日：1971-07-20

    申请号：US3594561D

    申请日：1968-11-04

    申请人： ARTHUR L WHITWELL

    发明人： WHITWELL ARTHUR L

    IPC分类号： G06F7/491 ,  G06F7/50 ,  G06F7/44

    CPC分类号： G06F7/4912 ,  G06F2207/49195

    摘要： An arrangement for adding together two n-digit decimal numbers or subtracting one n-digit decimal number from another comprises 10-condition switch means, the 10 conditions corresponding respectively to digits in the range 0 to 9 to be added or subtracted, and means to determine the need for and to implement the necessary carries.