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68 条记录 (耗时 0.027 秒)

    Booth's conversion circuit
    1.
    发明授权
    Booth's conversion circuit 失效
    展位的转换电路

    公开(公告)号：US4798980A

    公开(公告)日：1989-01-17

    申请号：US49141

    申请日：1987-05-13

    申请人： Hisashi Sugiyama ,  Yasuhiro Sugimoto ,  Yukio Kamatani

    发明人： Hisashi Sugiyama ,  Yasuhiro Sugimoto ,  Yukio Kamatani

    IPC分类号： G06F7/53 ,  G06F7/44 ,  G06F7/52 ,  G06F7/533 ,  H03K19/21 ,  H03K19/017 ,  H03K19/094

    CPC分类号： G06F7/5332

    摘要： A Booth's algorithm conversion circuit having first and second switches controlled by input signals QX and Q2X and receiving as input, signals X.sub.i of a logic level positioned in the i digit order of a multiplicand X and signal X.sub.i-1 of a logic level positioned in the i-1 digit order of multiplicand X. The outputs of the first and second switches are tied together and to ground via first and second transitors controlled by signals QX and Q2X, the first and second transistors conducting in an inverse relationship to the first and second switch circuits. The common output of the first and second switch circuits is input to an exclusive OR circuit which receives an additional logic 1 or logic 0 input signal to produce the Booth's converted output. The resulting number of circuit elements and gates provides a simplified, high speed and small circuit for producing the Booth's conversion.

    摘要翻译： 一种展位的算法转换电路，具有由输入信号QX和Q2X控制的第一和第二开关，并且接收位于被乘数X的i数位顺序的逻辑电平的信号Xi和位于该位置的逻辑电平的信号Xi-1 被乘数X的i-1位数。第一和第二开关的输出通过由信号QX和Q2X控制的第一和第二转换器连接在一起并接地，第一和第二晶体管与第一和第二开关反向关系 开关电路。 第一和第二开关电路的公共输出被输入到异或电路，该异或电路接收额外的逻辑1或逻辑0输入信号以产生布斯的转换输出。 所产生的电路元件和门的数量提供了简化的高速和小电路，用于生产Booth的转换。

    Full adder circuit using differential transistor pairs
    2.
    发明授权
    Full adder circuit using differential transistor pairs 失效
    全加器电路使用差分晶体管对

    公开(公告)号：US4740907A

    公开(公告)日：1988-04-26

    申请号：US716090

    申请日：1985-03-26

    申请人： Shoichi Shimizu ,  Yukio Kamatani ,  Yasuhiro Sugimoto ,  Hiroyuki Hara

    发明人： Shoichi Shimizu ,  Yukio Kamatani ,  Yasuhiro Sugimoto ,  Hiroyuki Hara

    IPC分类号： G06F7/501 ,  G06F7/50 ,  G06F7/503

    CPC分类号： G06F7/5016 ,  G06F7/501 ,  G06F2207/4806

    摘要： A high-speed full adder circuit comprising a plurality of differential transistor pairs and operating at multiple logic levels. This full adder can be made up of basic logic circuits, each having differential transistor pairs, such as exclusive-OR circuits, AND circuits and OR circuits. To reduce the chip size of the full adder, while ensuring a high-speed operation, transistors which may be used in common are replaced by a smaller number of transistors, thereby reducing the number of required transistors.

    摘要翻译： 一种包括多个差分晶体管对并以多个逻辑电平工作的高速全加器电路。 这个全加器可以由各自具有差分晶体管对的基本逻辑电路组成，例如异或电路，AND电路和OR电路。 为了减小全加器的芯片尺寸，在确保高速运行的同时，可以共同使用的晶体管被​​更少数量的晶体管代替，从而减少所需晶体管的数量。

    Analog/digital converter circuit
    3.
    发明授权
    Analog/digital converter circuit 失效
    模/数转换电路

    公开(公告)号：US4918450A

    公开(公告)日：1990-04-17

    申请号：US367654

    申请日：1989-06-19

    申请人： Hisashi Sugiyama ,  Yasuhiro Sugimoto

    发明人： Hisashi Sugiyama ,  Yasuhiro Sugimoto

    IPC分类号： H03M1/36 ,  H03M1/12

    CPC分类号： H03M1/1295 ,  H03M1/365

    摘要： An analog/digital converter circuit including a capacitor having a first end, to which an analog voltage is applied, and a second end, an input buffer circuit having an input terminal, connected to the second end of said capacitor, and an output terminal, a reference voltage generating circuit for generating a plurality of reference voltages having different voltage levels, a voltage comparator circuit having a plurality of voltage comparators for comparing the output voltage of the input buffer circuit with each of the reference voltages generated by the reference voltage generating circuit, and generating a digital signal corresponding to the comparison results, a decoder circuit for decoding the output of the voltage comparator circuit, and D.C. bias voltage selection/supply circuit for selecting one of the reference voltages of the reference voltage generating circuit and supplying the selected reference voltage as a D.C. bias voltage to the input terminal of the input buffer circuit.

    摘要翻译： 一种模拟/数字转换器电路，包括具有施加模拟电压的第一端和第二端的电容器，具有连接到所述电容器的第二端的输入端子的输入缓冲电路和输出端子， 用于产生具有不同电压电平的多个参考电压的参考电压产生电路，具有多个电压比较器的电压比较器电路，用于将输入缓冲器电路的输出电压与由参考电压产生电路产生的每个参考电压进行比较 并产生与比较结果相对应的数字信号，用于对电压比较器电路的输出进行解码的解码器电路以及用于选择参考电压发生电路的参考电压之一并提供所选择的电压的直流偏置电压选择/供给电路 参考电压作为直流偏置电压输入到输入缓冲器的输入端 它。

    Level conversion circuit
    4.
    发明授权
    Level conversion circuit 失效
    电平转换电路

    公开(公告)号：US4779016A

    公开(公告)日：1988-10-18

    申请号：US849

    申请日：1987-01-06

    申请人： Hisashi Sugiyama ,  Yasuhiro Sugimoto

    发明人： Hisashi Sugiyama ,  Yasuhiro Sugimoto

    IPC分类号： H03K19/0175 ,  H03K19/018 ,  H03K19/0944 ,  H03K19/092 ,  H03K19/094

    CPC分类号： H03K19/09448 ,  H03K19/017527

    摘要： Level conversion circuit for converting ECL logic level signals to CMOS logic level signals. The level conversion circuit includes: a differential amplifier circuit, which has a bipolar transistor of which the base terminal is connected to an input terminal and a bipolar transistor of which the base terminal is connected to a bias source, and which selects a current path from a high voltage source to a low voltage source; an MOS type transistor whose conduction is controlled by current flowing through the collector terminal of one of said bipolar transistors; a P-channel MOS type transistor, connected between the high voltage source and an output terminal, whose conduction is controlled either by the collector terminal current flowing through the collector terminal of the other of said bipolar transistors or by the drain terminal current flowing between the source termial and the drain terminal of said MOS transistor; and an N-channel MOS type transitor, connected between the low voltage source and the output terminal, whose conduction is controlled either said collector terminal current or by said drain terminal current.

    摘要翻译： 电平转换电路，用于将ECL逻辑电平信号转换为CMOS逻辑电平信号。 电平转换电路包括：差分放大器电路，其具有基极端子连接到输入端子的双极晶体管和基极端子连接到偏置源的双极晶体管，并且其选择来自 将高电压源提供给低电压源; MOS晶体管，其导通通过流过所述双极晶体管之一的集电极端子的电流来控制; 连接在高电压源和输出端子之间的P沟道MOS型晶体管，其导通由流过所述双极晶体管的另一个的集电极端子的集电极端电流或通过在 所述MOS晶体管的源极端子和漏极端子; 以及连接在低电压源和输出端子之间的N沟道型MOS晶体管，其导通被控制在集电极端子电流或所述漏极端子电流之间。

    Logic circuit for use in D/A converter having ECL-type gate structure
    5.
    发明授权
    Logic circuit for use in D/A converter having ECL-type gate structure 失效
    用于具有ECL型栅极结构的D / A转换器的逻辑电路

    公开(公告)号：US5034630A

    公开(公告)日：1991-07-23

    申请号：US476539

    申请日：1990-02-07

    申请人： Hisashi Sugiyama ,  Michinori Nakamura ,  Yasuhiro Sugimoto

    发明人： Hisashi Sugiyama ,  Michinori Nakamura ,  Yasuhiro Sugimoto

    IPC分类号： H03K19/086 ,  H03M7/00 ,  H03M7/14 ,  H03M7/16

    CPC分类号： H03M7/14 ,  H03K19/0866 ,  H03M7/165

    摘要： A logic circuit outputs state signals of seven different kinds, on the basis of first, second and third digital signals. A first composite gate circuit outputs a logical OR among the first to third digital signals as a first state signal. A first gate circuit outputs a logical OR between the second and third digital signals as a second state signal. A second composite gate circuit is supplied with a logical AND between the first and second digital signals, and outputs a logical OR between the supplied logical AND and the third digital signal as third state signal. A third composite gate circuit is supplied with a logical OR between the first and second digital signals, and outputs a logical AND between the supplied logical OR and the third digital signal as a fifth state signal. A second gate circuit outputs a logical AND between the second and third digital signals as a sixth state signal. A fourth composite gate circuit is supplied with a logical AND between the first and second digital signals, and outputs a logical AND between the supplied logical AND and the third digital signal as a seventh state signal. The third digital signal is output as a fourth state signal without being processed. Each of the above circuits has an emitter coupled logic structure.

    Ceramic capacitor
    6.
    发明授权
    Ceramic capacitor 有权
    陶瓷电容器

    公开(公告)号：US07889509B2

    公开(公告)日：2011-02-15

    申请号：US11513039

    申请日：2006-08-31

    申请人： Kazuhiro Urashima ,  Shinji Yuri ,  Manabu Sato ,  Yasuhiro Sugimoto

    发明人： Kazuhiro Urashima ,  Shinji Yuri ,  Manabu Sato ,  Yasuhiro Sugimoto

    IPC分类号： H05K7/00

    CPC分类号： H05K1/185 ,  H01G2/06 ,  H01G4/385 ,  H01L23/49816 ,  H01L23/50 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/3025 ,  H05K1/0231 ,  H05K3/4602 ,  H05K2201/10045 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2224/05599

    摘要： A circuit board (10, 10″, 10′″) comprising: a board core (11) having a main core surface (12) and a rear core surface (13); a ceramic capacitor (101, 101′, 101″, 101′″, 101″″, 101″″′, 101″″″) having a main capacitor surface (102) and a rear capacitor surface (103), having a structure in which a first inner electrode layer (141) and a second inner electrode layer (142) are alternately stacked with a ceramic dielectric layer (105) interposed therebetween, and having a plurality of capacitor function units (107, 108) being electrically independent from each other, the ceramic capacitor (101, 101′, 101″, 101′″, 101″″, 101″″′, 101″″″) being buried in the board core (11) in a state where the main core surface (12) and the main capacitor surface (102) are directed in a same direction; and a buildup layer (31) having a structure in which an interlayer insulating layer (33, 35) and a conductor layer (42) are alternately stacked on the main core surface (12) and the main capacitor surface (102) and having a semiconductor integrated circuit device mounting region (23, 51, 52) for mounting a semiconductor integrated circuit device (21, 53, 54) having a plurality of processor cores (24, 25) on a surface (39) of the buildup layer (31), wherein the plurality of capacitor function units (107, 108) are capable of being electrically connected to the plurality of processor cores (24, 25), respectively.

    摘要翻译： 一种电路板（10,10“，10”），包括：具有主芯表面（12）和后芯表面（13）的板芯（11）; 具有主电容器表面（102）和后电容器表面（103）的陶瓷电容器（101,101'，101“，101”，101“”，101“”，101“”“）， 其中第一内部电极层（141）和第二内部电极层（142）交替层叠有介于其间的陶瓷介电层（105），并且具有多个电容器功能单元（107,108），其电独立于 相互之间的陶瓷电容器（101,101'，101“，101”，101“，101”，101“”101“”）被埋在板芯11中， （12）和主电容器表面（102）指向相同的方向; 以及具有层间绝缘层（33,35）和导体层（42）在主芯面（12）和主电容器表面（102）上交替层叠的结构的积层（31），具有 半导体集成电路器件安装区域（23,51,52），用于安装具有多个处理器核心（24,25）的半导体集成电路器件（21,53,54），所述多个处理器核心（24,25）在所述生成层（31）的表面（39）上 ），其中所述多个电容器功能单元（107,108）能够分别电连接到所述多个处理器核（24,25）。

    Wiring board providing impedance matching
    7.
    发明授权
    Wiring board providing impedance matching 有权
    接线板提供阻抗匹配

    公开(公告)号：US07339260B2

    公开(公告)日：2008-03-04

    申请号：US10927134

    申请日：2004-08-27

    申请人： Yasuhiro Sugimoto ,  Kazunaga Higo ,  Kazuhiro Suzuki

    发明人： Yasuhiro Sugimoto ,  Kazunaga Higo ,  Kazuhiro Suzuki

    IPC分类号： H01L23/12 ,  H01L23/02 ,  H05K3/46 ,  H05K1/02 ,  H01H29/40

    CPC分类号： H01L23/66 ,  H01L2224/16 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0222 ,  H05K1/0251 ,  H05K1/113 ,  H05K3/4602 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09618 ,  H05K2201/09627 ,  H05K2201/0969 ,  H05K2201/09718 ,  H05K2201/09809

    摘要： A wiring board comprising: a plate core having a first main surface and a second main surface; conductor layers including a conductor line; dielectric layers laminated alternately with said conductor layers on at least one of said first and second main surfaces; via conductors as defined herein; a signal through-hole as defined herein; a signal through-hole conductor as defined herein; a first path end pad as defined herein; a second path end pad as defined herein; a shield through-hole as defined herein; and a shield through-hole conductor as defined herein; wherein: a signal transmission path is formed as defined herein; at least one of said conductor layers is disposed on each of said first and second main surface sides; said surface conductor on said first main surface side and said conductor line form a strip line, a microstrip line, or a coplanar waveguide with constant characteristic impedance Z0; an inner surface of said shield through-hole is covered with said shield through-hole conductor; and an interaxis distance between said signal through-hole conductor and said shield through-hole conductor is adjusted as defined herein.

    摘要翻译： 一种布线板，包括：板芯，具有第一主表面和第二主表面; 包括导体线的导体层; 电介质层与所述导体层交替地层叠在所述第一和第二主表面中的至少一个上; 通孔导体; 如本文所定义的信号通孔; 如本文所定义的信号通孔导体; 如本文所定义的第一路径端垫; 如本文所定义的第二路径端垫; 如本文所定义的屏蔽通孔; 和如本文所定义的屏蔽通孔导体; 其中：如本文所定义的形成信号传输路径; 所述导体层中的至少一个设置在所述第一和第二主表面侧的每一个上; 所述第一主表面侧的所述表面导体和所述导体线形成具有恒定特性阻抗Z 0的带状线，微带线或共面波导; 所述屏蔽通孔的内表面被所述屏蔽通孔导体覆盖; 并且如本文所定义的那样调整所述信号通孔导体和所述屏蔽通孔导体之间的间隔距离。