公开(公告)号：US20230412864A1

公开(公告)日：2023-12-21

申请号：US17845377

申请日：2022-06-21

Applicant: ATI Technologies ULC

Inventor： Marvin Younan ,  Ihab Amer ,  Feng Pan

IPC: H04N21/2662 ,  H04N19/117 ,  H04N19/136 ,  H04N21/24

CPC classification number: H04N21/2662 ,  H04N19/117 ,  H04N19/136 ,  H04N21/2402

Abstract: Adaptive digital content preprocessing techniques based on a bitrate are described. In an implementation, a parameter of a preprocessing module is set based on a target bitrate. The parameter specifies an amount of preprocessing to be performed in preprocessing digital content. Preprocessed digital content is generated by preprocessing the digital content by the specified amount using the preprocessing module. Encoded digital content is generated by compressing the preprocessed digital content using a compression technique by an encoder. The encoded digital content is then transmitted for communication at the target bitrate.

公开(公告)号：US11848656B2

公开(公告)日：2023-12-19

申请号：US17357277

申请日：2021-06-24

Applicant: ATI Technologies ULC

Inventor： Fei Guo

IPC: H03H7/20 ,  H03K5/1252 ,  H01L23/66 ,  H01L23/498

CPC classification number: H03H7/20 ,  H01L23/49827 ,  H01L23/66 ,  H03K5/1252

Abstract: A power delivery network, circuit, and method reduce die package resonance of an integrated circuit (IC) die. Decoupling capacitors interact with equivalent series inductances (ESLs) of power conductors within a package carrier substrate create the die package resonance characteristic. In one form an anti-resonance tuning circuit has a first branch including a first inductance coupled to one of an IC die positive power supply conductor and an IC die negative power supply conductor, and a second branch coupled directly to a selected one of a carrier substrate positive or negative conductive structures, the second branch comprising a second inductance inductively coupled to the first inductance.

公开(公告)号：US20230403415A1

公开(公告)日：2023-12-14

申请号：US17838552

申请日：2022-06-13

Applicant: Advanced Micro Devices, Inc ,  ATI Technologies ULC

Inventor： Ihab Amer ,  Gabor Sines ,  Haibo Liu ,  Khaled Mammou ,  Arun Sundaresan Iyer

IPC: H04N21/2343 ,  H04N21/4402 ,  H04N21/442

CPC classification number: H04N21/2343 ,  H04N21/4402 ,  H04N21/44209

Abstract: Adaptive decoder-drive encoder reconfiguration techniques are described. In one example, techniques include detecting an operational condition at a consumer using a sensor, the consumer receiving a communication of digital content from an encoder; generating an adaptation instruction by the decoder based on the detecting; transmitting the adaptation instruction by the decoder for receipt by the encoder; and receiving an adapted communication of the digital content generated by the encoder, the adapted communication caused by reconfiguration of the encoder based on the adaptation instruction received from the decoder.

公开(公告)号：US11831900B2

公开(公告)日：2023-11-28

申请号：US17215347

申请日：2021-03-29

Applicant: ATI Technologies ULC

Inventor： Haibo Liu ,  Ihab Amer

IPC: H04N19/52 ,  H04N19/176 ,  H04N19/172 ,  H04N19/182 ,  H04N19/136 ,  H04N19/593

CPC classification number: H04N19/52 ,  H04N19/136 ,  H04N19/172 ,  H04N19/176 ,  H04N19/182 ,  H04N19/593

Abstract: Methods and apparatus encode image frames using intra-frame prediction by predicting pixels for a block of current pixels, based on a detected spatial pattern of pixel intensity differences among a plurality of neighboring reconstructed pixels to the block of current pixels, and encode a block of pixels of the image frame using the predicted block of reconstructed pixels. Inter-frame prediction is provided by determining whether blocks of pixels in temporally neighboring reconstructed frames corresponding to a candidate motion vector have a pattern of pixel intensity differences among the blocks from temporally neighboring frames. Predicted blocks are produced for a reconstructed frame based on the determined pattern of pixel intensity difference among temporally neighboring frames.

公开(公告)号：US11830225B2

公开(公告)日：2023-11-28

申请号：US15993074

申请日：2018-05-30

Applicant: ATI TECHNOLOGIES ULC

Inventor： Yang Liu ,  Ihab Amer ,  Gabor Sines ,  Boris Ivanovic ,  Jinbo Qiu

IPC: G06T9/00 ,  G06T15/00

CPC classification number: G06T9/00 ,  G06T15/005 ,  G06T2210/08 ,  G06T2210/36

Abstract: A feedback processing module includes a memory configured to store feedback received from an encoder. The feedback includes parameters associated with encoded graphics content generated by a graphics engine. The feedback processing module also includes a processor configured to generate configuration information for the graphics engine based on the feedback. The graphics engine is configured to execute a workload based on the configuration information. In some cases, the feedback processing module is also configured to receive feedback from a decoder that is used to decode the graphics content that is encoded by the encoder and generate the configuration information based on the feedback received from the decoder.

公开(公告)号：US20230367730A1

公开(公告)日：2023-11-16

申请号：US17743848

申请日：2022-05-13

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： YULEI SHEN ,  TYRONE TUNG HUANG ,  CHEN-KUAN HONG

IPC: G06F13/40 ,  G06F13/20 ,  H01L25/065 ,  H01L23/538

CPC classification number: G06F13/4031 ,  G06F13/20 ,  H01L23/5382 ,  H01L25/0655 ,  H01L24/16 ,  H01L2924/1431

Abstract: A semiconductor package includes multiple dies that share the same package pin. An output enable register provided on each die is used to select the die that drives an output to the shared pin. A hardware arbitration circuit ensures that two or more dies do not drive an output to the shared pin at the same time.

公开(公告)号：US20230315625A1

公开(公告)日：2023-10-05

申请号：US18331754

申请日：2023-06-08

Applicant: ATI TECHNOLOGIES ULC

Inventor： NIPPON RAVAL ,  PHILIP NG ,  ROSTISLAV S. DOBRIN

IPC: G06F12/06 ,  G06F13/28 ,  G06F13/42

CPC classification number: G06F12/063 ,  G06F13/28 ,  G06F13/4221 ,  G06F2212/206

Abstract: Methods, systems, and apparatuses provide support for multiple address spaces in order to facilitate data movement. One apparatus includes an input/output memory management unit (IOMMU) comprising: a plurality of memory-mapped input/output (MMIO) registers that map memory address spaces belonging to the IOMMU and at least a second IOMMU; and hardware control logic operative to: synchronize the plurality of MMIO registers of the at least the second IOMMU; receive, from a peripheral component endpoint coupled to the IOMMU, a direct memory access (DMA) request, the DMA request to a memory address space belonging to the at least the second IOMMU; access the plurality of MMIO registers of the IOMMU based on context data of the DMA request; and access, from the IOMMU, a function assigned to the memory address space belonging to the at least the second IOMMU based on the accessed plurality of MMIO registers.

公开(公告)号：US20230298256A1

公开(公告)日：2023-09-21

申请号：US17844677

申请日：2022-06-20

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Daniel James Skinner ,  Michael John Livesley ,  David William John Pankratz

IPC: G06T15/06 ,  G06T15/08 ,  G06T17/10

CPC classification number: G06T15/06 ,  G06T15/08 ,  G06T17/10 ,  G06T2210/21

Abstract: A technique for performing ray tracing operations is provided. The technique includes, in response to detecting that a threshold number of traversal stage work-items of a wavefront have terminated, increasing intersection test parallelization for non-terminated work-items.

公开(公告)号：US20230298133A1

公开(公告)日：2023-09-21

申请号：US17976192

申请日：2022-10-28

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Steven Tovey ,  Jimmy Stefan Petersson ,  Thomas Arcila ,  Zhuo Chen ,  Stephan Hodes ,  Colin Riley ,  Sylvain Daniel Julien Meunier

IPC: G06T3/40 ,  G06T7/246

CPC classification number: G06T3/4053 ,  G06T7/248

Abstract: A first frame of a video stream rendered at a first resolution is obtained. A second frame of the video stream upscaled to a second higher resolution is also obtained. The first plurality of pixels is upscaled to the second resolution. The upsampling generates upsampled color data for the upsampled first plurality of pixels. The upsampled color data is accumulated with a second set of color data associated with a second plurality of pixels defining the second frame to generate final color data for the upsampled first plurality of pixels. Color data of the second set of color data associated with a pixel lock contributes more to the final color data than corresponding color data of the upsampled color data. The upsampled first plurality of pixels is stored with the final color data as an upscaled frame representing the first frame at the second resolution.

公开(公告)号：US11763778B2

公开(公告)日：2023-09-19

申请号：US17884793

申请日：2022-08-10

Applicant: ATI TECHNOLOGIES ULC

Inventor： David I. J. Glen

IPC: G09G5/36 ,  G09G3/20

CPC classification number: G09G5/363 ,  G09G3/20 ,  G09G2310/061 ,  G09G2310/08

Abstract: A graphics processing unit (GPU) includes a timing reference one or more processors configured to generate and provide, based on the timing reference, frames to a display system that supports variable refresh rates. The frames include a vertical blanking region having a first duration. The display system transmits information indicating an operation to be performed by the display system during the vertical blanking region of one or more subsequent frames. The one or more processors are configured to increase the first duration to a second duration in response to receiving the information indicating an operation to be performed by the display system during the vertical blanking region of at least one subsequent frame. In some cases, the first duration of the vertical blanking region is a minimum duration that corresponds to a maximum refresh rate supported by the display system.