公开(公告)号：US12075525B2

公开(公告)日：2024-08-27

申请号：US17310332

申请日：2020-01-09

Applicant: ARM IP LIMITED ,  ARM LIMITED

Inventor： Mikko Johannes Saarnivala ,  Szymon Sasin ,  Yongbeom Pak ,  Hannes Tschofenig

IPC: H04W8/24 ,  H04W4/70 ,  H04W8/02 ,  H04W28/18 ,  H04W60/00

CPC classification number: H04W8/245 ,  H04W4/70 ,  H04W8/02 ,  H04W28/18 ,  H04W60/00

Abstract: Broadly speaking, the present techniques relate to a computer implemented method for enabling template-based registration, the method performed by an intermediary apparatus in communication with a first device and a server, the method comprising: receiving, from the first device, a registration request comprising one or more device identifiers for the first device; determining the availability of template information for the first device based on or in response to the one or more device identifiers; when the template information for the first device is unavailable: generating template information for the first device; or requesting, from the server, the template information.

公开(公告)号：US12073641B2

公开(公告)日：2024-08-27

申请号：US17219721

申请日：2021-03-31

Applicant: Arm Limited

Inventor： Renee Marie St. Amant

IPC: G06V20/80 ,  G02B27/01 ,  G06F3/01 ,  G06F16/58 ,  G06F16/587 ,  G06Q20/32

CPC classification number: G06V20/80 ,  G02B27/0172 ,  G06F3/013 ,  G06F16/5866 ,  G06F16/587 ,  G06Q20/321 ,  G06Q20/3276 ,  G02B2027/0138 ,  G02B2027/014

Abstract: Subject matter disclosed herein relates to systems, devices, and/or processes for processing signals relating to surfaces that may be viewable by subjects though one or more devices. In an embodiment, a surface may include one or more devices embedded therein to provide one or more signals to define a portion of the surface.

公开(公告)号：US12073640B2

公开(公告)日：2024-08-27

申请号：US17219707

申请日：2021-03-31

Applicant: Arm Limited

Inventor： Renee Marie St. Amant

IPC: G06V20/80 ,  G02B27/01 ,  G06N20/00 ,  G06Q20/32 ,  G06V20/20

CPC classification number: G06V20/80 ,  G02B27/0172 ,  G06N20/00 ,  G06Q20/321 ,  G06Q20/3276 ,  G06V20/20 ,  G02B2027/0138 ,  G02B2027/014

Abstract: Subject matter disclosed herein relates to systems, devices, and/or processes for processing signals relating to surfaces that may be viewable by subjects though one or more devices. In an embodiment, a surface may include one or more devices embedded therein to provide one or more signals to define a portion of the surface.

公开(公告)号：US12073104B1

公开(公告)日：2024-08-27

申请号：US18299763

申请日：2023-04-13

Applicant: Arm Limited

Inventor： Roberto Avanzi ,  Andreas Lars Sandberg ,  David Helmut Schall

IPC: G06F3/06

CPC classification number: G06F3/0644 ,  G06F3/0623 ,  G06F3/0673

Abstract: There is provided a memory protection unit configured to maintain region metadata associated with storage regions of off-chip storage and protection metadata associated with each of the storage regions. The protection metadata is stored in the off-chip storage, and the region metadata encodes whether each of the storage regions belongs to a set of protected storage regions or to a set of unprotected storage regions and encodes information indicating corresponding protection metadata associated with each storage region. The memory protection unit is configured to update the region metadata in response to a region update request identifying a given storage region for which the region metadata is to be modified and to dynamically adjust an amount of memory required to store protection metadata associated with the set of protected storage regions in response to the update to the region metadata.

公开(公告)号：US12066855B2

公开(公告)日：2024-08-20

申请号：US18091719

申请日：2022-12-30

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan ,  Akash Bangalore Srinivasa ,  Munish Kumar ,  Khushal Gelda ,  Akshay Kumar

IPC: G06F1/00 ,  G06F1/06 ,  G06F1/10 ,  G06F11/30

CPC classification number: G06F1/10 ,  G06F1/06 ,  G06F11/3062

Abstract: Various implementations described herein are related to a device having multi-port circuit architecture with multiple ports. The multi-port circuit architecture may expand a primary clock into multiple dummy clocks so as to separately track, simulate and report clock power consumption for each port of the multiple ports to a central processing unit.

公开(公告)号：US12057947B1

公开(公告)日：2024-08-06

申请号：US18115301

申请日：2023-02-28

Applicant: Arm Limited

Inventor： Sean Allan Steel ,  David Yue Williams ,  Premkishore Shivakumar

IPC: H04L1/00 ,  H04L1/24

CPC classification number: H04L1/245

Abstract: In a data processing network, error detection information (EDI) is generated for first data of a first communication protocol of a plurality of communication protocols, the EDI including an error detection code and an associated validity indicator for each field group in a set of field groups. The first data and the EDI are sent through a network interconnect circuit, where the first data is translated to second data of a second communication protocol. An error is detected in the second data received from the network interconnect circuit when a validity indicator for a field group is set in EDI received with the second data and an error detection code generated for second data in the field group does not match the error detection code associated with the field group in the received EDI.

公开(公告)号：US12056058B2

公开(公告)日：2024-08-06

申请号：US17850072

申请日：2022-06-27

Applicant: Arm Limited

Inventor： Andrew David Tune ,  Andrew Brookfield Swaine

IPC: G06F12/121 ,  G06F12/06 ,  G06F12/0891

CPC classification number: G06F12/121 ,  G06F12/0646 ,  G06F12/0891

Abstract: An apparatus comprises a cache comprising a plurality of cache entries, and cache replacement control circuitry to select, in response to a cache request specifying a target address missing in the cache, a victim cache entry to be replaced with a new cache entry. The cache request specifies a partition identifier indicative of an execution environment associated with the cache request. The victim cache entry is selected based on re-reference interval prediction (RRIP) values for a candidate set of cache entries. The RRIP value for a given cache entry is indicative of a relative priority with which the given cache entry is to be selected as the victim cache entry. Configurable replacement policy configuration data is selected based on the partition identifier, and the RRIP value of the new cache entry is set to an initial value selected based on the selected configurable replacement policy configuration data.

公开(公告)号：US20240260261A1

公开(公告)日：2024-08-01

申请号：US18103316

申请日：2023-01-30

Applicant: Arm Limited

Inventor： Yannick Marc Nevers ,  Valerio Lanieri ,  Amit Chhabra

IPC: H10B20/00

CPC classification number: H10B20/50 ,  H10B20/34

Abstract: Various implementations described herein are related to a device having a memory architecture with a multi-stack of transistors that may be arranged in a multi-bitcell stack configuration. Also, the memory architecture may have a wordline that may be shared across the transistors of the multi-stack of transistors with each transistor coupled to a different bitline.

公开(公告)号：US20240257432A1

公开(公告)日：2024-08-01

申请号：US18103937

申请日：2023-01-31

Applicant: Arm Limited

Inventor： Derek Andrew LAMBERTI ,  Kévin PETIT ,  Thomas James COOKSEY

IPC: G06T15/00 ,  G06T15/04

CPC classification number: G06T15/005 ,  G06T15/04

Abstract: A method is provided for generating a mipmap. A processor comprises a neural processing engine comprising a plurality of hardware units suitable for performing integer operations on machine learning models. The method comprises receiving initial image data and one or more commands to perform an operation for generating a further layer of image data from the initial image data that has a different resolution to the initial image data. The method processes the commands to generate the further layer using the neural processing engine of the processor.

公开(公告)号：US20240256436A1

公开(公告)日：2024-08-01

申请号：US18162491

申请日：2023-01-31

Applicant: Arm Limited

Inventor： Kévin Petit

IPC: G06F12/02 ,  G06F9/48

CPC classification number: G06F12/023 ,  G06F9/4881 ,  G06F2212/251

Abstract: A system, method and computer program product configured to control a plurality of parallel programs operating in an n-dimensional hierarchical iteration space over an n-dimensional data space, comprising: a processor and a memory configured to accommodate the plurality of parallel programs and the data space; a memory access control decoder configured to decode memory location references to regions of the n-dimensional data space from indices in the plurality of parallel programs; and an execution orchestrator responsive to the memory access control decoder and configured to sequence regions of the n-dimensional hierarchical iteration space of the plurality of parallel programs to honour a data requirement of at least a first of the plurality of parallel programs having a data dependency on at least a second of the plurality of parallel programs.