公开(公告)号：US07238989B2

公开(公告)日：2007-07-03

申请号：US11201990

申请日：2005-08-11

Applicant: Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Mong-Song Liang ,  Chenming Hu

Inventor： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Mong-Song Liang ,  Chenming Hu

IPC: H01L27/01

CPC classification number: H01L29/1054 ,  H01L21/84 ,  H01L27/1203

Abstract: A method of fabricating a CMOS device wherein mobility enhancement of both the NMOS and PMOS elements is realized via strain induced band structure modification, has been developed. The NMOS element is formed featuring a silicon channel region under biaxial strain while the PMOS element is simultaneously formed featuring a SiGe channel region under biaxial compressive strain. A novel process sequence allowing formation of a thicker silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer which is under biaxial tensile strain enhancing electron mobility. The same novel process sequence results in the presence of a thinner silicon layer, overlying the same SiGe layer in the PMOS region, allowing the PMOS channel region to exist in the biaxial compressively strained SiGe layer, resulting in hole mobility enhancement.

Abstract translation: 已经开发了通过应变诱导带结构修改来实现NMOS和PMOS元件的迁移率增强的CMOS器件的制造方法。 NMOS元件形成为具有双轴应变下的硅沟道区，同时形成在双轴压缩应变下具有SiGe沟道区的PMOS元件。 允许形成覆盖SiGe层的较厚硅层的新颖工艺顺序允许NMOS沟道区存在于覆盖SiGe层的硅层中，允许NMOS沟道区存在于双层拉伸应变增强下的硅层中 电子迁移率。 相同的新工艺序列导致存在较薄的硅层，覆盖PMOS区域中相同的SiGe层，允许PMOS沟道区存在于双轴压缩应变SiGe层中，导致空穴迁移率增强。

公开(公告)号：US07202122B2

公开(公告)日：2007-04-10

申请号：US10710012

申请日：2004-06-11

Applicant: Chien-Chao Huang ,  Yee-Chia Yeo ,  Chao-Hsiung Wang ,  Chun-Chieh Lin ,  Chenming Hu

Inventor： Chien-Chao Huang ,  Yee-Chia Yeo ,  Chao-Hsiung Wang ,  Chun-Chieh Lin ,  Chenming Hu

IPC: H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/66545 ,  Y10S438/933

Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

Abstract translation: 一种方法包括在半导体衬底上提供半导体合金层，在半导体合金层上形成栅极结构，在半导体衬底的栅极结构的两侧形成源区和漏极区，去除半导体合金层的至少一部分 覆盖源极和漏极区域，并且在源极和漏极区域上形成金属硅化物区域。

公开(公告)号：US07183593B2

公开(公告)日：2007-02-27

申请号：US10745831

申请日：2003-12-24

Applicant: Yee-Chia Yeo ,  Wen-Chin Lee ,  Chih-Hsin Ko ,  Chung-Hu Ge ,  Chun-Chieh Lin ,  Chenming Hu

Inventor： Yee-Chia Yeo ,  Wen-Chin Lee ,  Chih-Hsin Ko ,  Chung-Hu Ge ,  Chun-Chieh Lin ,  Chenming Hu

IPC: H01L29/86 ,  H01L29/205

CPC classification number: H01L27/0629 ,  H01L29/165 ,  H01L29/8605

Abstract: A heterostructure resistor comprises a doped region formed in a portion of a semiconductor substrate, the substrate comprising a first semiconductor material having a first natural lattice constant. The doped region comprises a semiconductor layer overlying the semiconductor substrate. The semiconductor layer comprises a second semiconductor material with a second natural lattice constant.

Abstract translation: 异质结构电阻器包括形成在半导体衬底的一部分中的掺杂区域，该衬底包括具有第一自然晶格常数的第一半导体材料。 掺杂区域包括覆盖半导体衬底的半导体层。 半导体层包括具有第二自然晶格常数的第二半导体材料。

公开(公告)号：US20060118878A1

公开(公告)日：2006-06-08

申请号：US11003844

申请日：2004-12-02

Applicant: Yi-Chun Huang ,  Hun-Jan Tao ,  Chun-Chieh Lin ,  Chih-Hsin Ko

Inventor： Yi-Chun Huang ,  Hun-Jan Tao ,  Chun-Chieh Lin ,  Chih-Hsin Ko

IPC: H01L29/94 ,  H01L21/8238

CPC classification number: H01L29/165 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: An NMOS and PMOS device pair having a selected stress level and type exerted on a respective channel region and method for forming the same, the method including providing a semiconductor substrate; forming isolation regions to separate active areas comprising a PMOS device region and an NMOS device region; lithographically patterning the semiconductor substrate and etching respective recessed areas including the respective NMOS and PMOS device regions into the silicon semiconductor substrate to a predetermined depth; backfilling the respective recessed areas with at least one semiconductor alloy; and, forming gate structures and offset spacers over the respective NMOS and PMOS device regions.

Abstract translation: 具有选择的应力水平和施加在相应沟道区上的类型的NMOS和PMOS器件对及其形成方法，所述方法包括提供半导体衬底; 形成隔离区以分离包括PMOS器件区和NMOS器件区的有源区; 将半导体衬底光刻图形化并将包括各个NMOS和PMOS器件区域的各个凹陷区域蚀刻到硅半导体衬底中至预定深度; 用至少一种半导体合金回填相应的凹陷区域; 以及在各个NMOS和PMOS器件区域上形成栅极结构和偏置间隔物。

公开(公告)号：US20060081875A1

公开(公告)日：2006-04-20

申请号：US10967917

申请日：2004-10-18

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

IPC: H01L31/109 ,  H01L31/0328 ,  H01L29/76

CPC classification number: H01L29/66636 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/802

Abstract: A transistor structure comprises a channel region overlying a substrate region. The substrate region comprises a first semiconductor material with a first lattice constant. The channel region comprises a second semiconductor material with a second lattice constant. The source and drain regions are oppositely adjacent the channel region and the top portion of the source and drain regions comprise the first semiconductor material. A gate dielectric layer overlies the channel region and a gate electrode overlies the gate dielectric layer.

Abstract translation: 晶体管结构包括覆盖衬底区域的沟道区域。 衬底区域包括具有第一晶格常数的第一半导体材料。 沟道区域包括具有第二晶格常数的第二半导体材料。 源极区和漏极区相对地邻近沟道区，并且源极和漏极区的顶部包括第一半导体材料。 栅极电介质层覆盖沟道区，栅电极覆盖在栅介质层上。

公开(公告)号：US20050272188A1

公开(公告)日：2005-12-08

申请号：US11201990

申请日：2005-08-11

Applicant: Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Mong-Song Liang ,  Chenming Hu

Inventor： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Mong-Song Liang ,  Chenming Hu

IPC: H01L21/00 ,  H01L21/84 ,  H01L27/12 ,  H01L31/109

CPC classification number: H01L29/1054 ,  H01L21/84 ,  H01L27/1203

Abstract: A method of fabricating a CMOS device wherein mobility enhancement of both the NMOS and PMOS elements is realized via strain induced band structure modification, has been developed. The NMOS element is formed featuring a silicon channel region under biaxial strain while the PMOS element is simultaneously formed featuring a SiGe channel region under biaxial compressive strain. A novel process sequence allowing formation of a thicker silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer which is under biaxial tensile strain enhancing electron mobility. The same novel process sequence results in the presence of a thinner silicon layer, overlying the same SiGe layer in the PMOS region, allowing the PMOS channel region to exist in the biaxial compressively strained SiGe layer, resulting in hole mobility enhancement.

Abstract translation: 已经开发了通过应变诱导带结构修改来实现NMOS和PMOS元件的迁移率增强的CMOS器件的制造方法。 NMOS元件形成为具有双轴应变下的硅沟道区，同时形成在双轴压缩应变下具有SiGe沟道区的PMOS元件。 允许形成覆盖SiGe层的较厚硅层的新颖工艺顺序允许NMOS沟道区存在于覆盖SiGe层的硅层中，允许NMOS沟道区存在于双层拉伸应变增强下的硅层中 电子迁移率。 相同的新工艺序列导致存在较薄的硅层，覆盖PMOS区域中相同的SiGe层，允许PMOS沟道区存在于双轴压缩应变SiGe层中，导致空穴迁移率增强。

公开(公告)号：US20050224850A1

公开(公告)日：2005-10-13

申请号：US10816730

申请日：2004-04-02

Applicant: Chun-Chieh Lin

Inventor： Chun-Chieh Lin

IPC: G11C11/15 ,  H01L21/8246 ,  H01L27/22 ,  H01L29/76 ,  H01L31/119 ,  H01L43/00

CPC classification number: H01L27/228 ,  B82Y10/00

Abstract: A magnetic random access memory (MRAM) device including a magnetic tunneling junction (MTJ) stack separated from one or more proximate conductive layers and/or one or more proximate MTJ stacks by a low-k dielectric material.

Abstract translation: 磁性随机存取存储器（MRAM）装置包括通过低k电介质材料从一个或多个邻近导电层和/或一个或多个邻近MTJ堆叠分离的磁隧道结（MTJ）堆叠。

公开(公告)号：US20050156208A1

公开(公告)日：2005-07-21

申请号：US10955349

申请日：2004-09-30

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

IPC: H01L21/336 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/76

CPC classification number: H01L29/665 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/785

Abstract: Provided are a semiconductor device and a method for its fabrication. In one example, the semiconductor device includes an active region formed on a substrate using a first silicide type and another active region formed on the substrate using another silicide type. The two silicide types differ and at least one of the two silicides is an alloy silicide. An etch stop layer may overlay at least one of the silicide regions.

Abstract translation: 提供半导体器件及其制造方法。 在一个示例中，半导体器件包括使用第一硅化物类型形成在衬底上的有源区和使用另一种硅化物类型形成在衬底上的另一有源区。 两种硅化物类型不同，并且两种硅化物中的至少一种是合金硅化物。 蚀刻停止层可覆盖至少一个硅化物区域。

公开(公告)号：US20050151166A1

公开(公告)日：2005-07-14

申请号：US10835100

申请日：2004-04-29

Applicant: Chun-Chieh Lin ,  Chih-Hsin Ko ,  Wen-Chin Lee

Inventor： Chun-Chieh Lin ,  Chih-Hsin Ko ,  Wen-Chin Lee

IPC: H01L21/336 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L27/092 ,  H01L27/10 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/76843 ,  H01L21/76877 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having a metal contact is provided. In the preferred embodiment, a metal contact is provided through an interlayer dielectric and is in electrical contact with a metal structure, such as a metal gate electrode of a transistor. A conductive layer is provided between the metal contact and the metal structure. The conductive layer provides one or more of a barrier layer, an adhesion layer, or an etch stop layer. The conductive layer is preferably an elemental metal, metal alloy, metal nitride, metal oxide, or a combination thereof. In an alternative embodiment, the conductive layer is formed of polysilicon.

Abstract translation: 提供具有金属接触的半导体器件。 在优选实施例中，通过层间电介质提供金属接触，并与诸如晶体管的金属栅电极的金属结构电接触。 在金属接触件和金属结构之间设置导电层。 导电层提供阻挡层，粘合层或蚀刻停止层中的一个或多个。 导电层优选为元素金属，金属合金，金属氮化物，金属氧化物或其组合。 在替代实施例中，导电层由多晶硅形成。

公开(公告)号：US20050145938A1

公开(公告)日：2005-07-07

申请号：US10749273

申请日：2003-12-29

Applicant: Chun-Chieh Lin

Inventor： Chun-Chieh Lin

IPC: H01L29/41 ,  H01L21/02 ,  H01L21/336 ,  H01L21/768 ,  H01L23/522 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/786 ,  H01L21/425

CPC classification number: H01L29/785 ,  H01L27/1203 ,  H01L29/41791 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66795 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A microelectronic device including an insulator located over a substrate, a semiconductor feature and a contact layer. The semiconductor feature has a thickness over the insulator, a first surface opposite the insulator, and a sidewall spanning at least a portion of the thickness. The contact layer has a first member extending over at least a portion of the first surface and a second member spanning at least a portion of the sidewall.