公开(公告)号：US20130271208A1

公开(公告)日：2013-10-17

申请号：US13977195

申请日：2011-12-19

Applicant: Han Wui Then ,  Robert Chau ,  Valluri Rao ,  Niloy Mukherjee ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Jack Kavalieros

Inventor： Han Wui Then ,  Robert Chau ,  Valluri Rao ,  Niloy Mukherjee ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Jack Kavalieros

IPC: H01L25/07 ,  H01L25/00

CPC classification number: H01L25/072 ,  H01L21/8252 ,  H01L21/8258 ,  H01L25/50 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) that is capable of achieving high Ft and also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits. In embodiments, the III-N transistor architecture is amenable to scaling to sustain a trajectory of performance improvements over many successive device generations. In embodiments, the III-N transistor architecture is amenable to monolithic integration with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. Planar and non-planar HEMT embodiments having one or more of recessed gates, symmetrical source and drain, regrown source/drains are formed with a replacement gate technique permitting enhancement mode operation and good gate passivation.

Abstract translation: 片上系统（SoC）解决方案使用基于能够实现高Ft和足够高击穿电压（BV）的III类氮化物（III-N）的晶体管技术将RFIC与PMIC集成，以实现高电压和/ 或高功率电路。 在实施例中，III-N晶体管架构适于缩放以维持许多连续器件世代的性能改进的轨迹。 在实施例中，III-N晶体管架构适于与IV类晶体管架构（诸如平面和非平面硅CMOS晶体管技术）的单片集成。 具有凹入栅极，对称源极和漏极，再生长源极/漏极中的一个或多个的平面和非平面HEMT实施例使用允许增强模式操作和良好栅极钝化的替代栅极技术形成。

公开(公告)号：US20130146945A1

公开(公告)日：2013-06-13

申请号：US13752272

申请日：2013-01-28

Applicant: Robert S. Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew Metz

Inventor： Robert S. Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew Metz

IPC: H01L29/267

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/201 ,  H01L29/207 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7836 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78681

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

公开(公告)号：US08344425B2

公开(公告)日：2013-01-01

申请号：US12655463

申请日：2009-12-30

Applicant: Marko Radosavljevic ,  Uday Shah ,  Gilbert Dewey ,  Niloy Mukherjee ,  Robert S. Chau ,  Jack Kavalieros ,  Ravi Pillarisetty ,  Titash Rakshit ,  Matthew V. Metz

Inventor： Marko Radosavljevic ,  Uday Shah ,  Gilbert Dewey ,  Niloy Mukherjee ,  Robert S. Chau ,  Jack Kavalieros ,  Ravi Pillarisetty ,  Titash Rakshit ,  Matthew V. Metz

IPC: H01L29/12 ,  H01L21/20 ,  H01L21/336 ,  H01L21/18

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7786 ,  H01L29/785

Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a III-V tri-gate fin on a substrate, forming a cladding material around the III-V tri-gate fin, and forming a hi k gate dielectric around the cladding material.

Abstract translation: 描述形成微电子结构的方法。 这些方法的实施例包括在基板上形成III-V三栅极翅片，在III-V三栅极鳍周围形成包层材料，以及在包层材料周围形成Hi栅极电介质。

公开(公告)号：US20120205729A1

公开(公告)日：2012-08-16

申请号：US13453403

申请日：2012-04-23

Applicant: Robert S. Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew Metz

Inventor： Robert S. Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew Metz

IPC: H01L29/772

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/201 ,  H01L29/207 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7836 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78681

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

Abstract translation: 描述具有窄带隙半导体源极/漏极区域的晶体管。 晶体管包括形成在形成于硅层上的栅介质层上的栅电极。 一对源极/漏极区域形成在栅电极的相对侧上，其中所述一对源极/漏极区域包括形成在栅电极的相对侧上的硅层中的窄带隙半导体膜。

公开(公告)号：US08148786B2

公开(公告)日：2012-04-03

申请号：US12493291

申请日：2009-06-29

Applicant: Jack Kavalieros ,  Annalisa Cappellani ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew V. Metz ,  Suman Datta ,  Chris E. Barns ,  Robert S. Chau

Inventor： Jack Kavalieros ,  Annalisa Cappellani ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew V. Metz ,  Suman Datta ,  Chris E. Barns ,  Robert S. Chau

IPC: H01L21/76

CPC classification number: H01L29/66636 ,  H01L21/28079 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/7834

Abstract: A complementary metal oxide semiconductor integrated circuit may be formed with a PMOS device formed using a replacement metal gate and a raised source drain. The raised source drain may be formed of epitaxially deposited silicon germanium material that is doped p-type. The replacement metal gate process results in a metal gate electrode and may involve the removal of a nitride etch stop layer.

Abstract translation: 互补金属氧化物半导体集成电路可以形成有使用替换金属栅极和升高源极漏极形成的PMOS器件。 凸起的源极漏极可以由掺杂p型的外延沉积的硅锗材料形成。 替代金属栅极工艺导致金属栅电极，并且可能涉及去除氮化物蚀刻停止层。

公开(公告)号：US20110312140A1

公开(公告)日：2011-12-22

申请号：US13216569

申请日：2011-08-24

Applicant: Ravi Pillarisetty ,  Jack Kavalieros ,  Marko Radosavljevic ,  Benjamin Chu-Kung

Inventor： Ravi Pillarisetty ,  Jack Kavalieros ,  Marko Radosavljevic ,  Benjamin Chu-Kung

IPC: H01L21/336

CPC classification number: H01L21/26586 ,  H01L29/0657 ,  H01L29/0834 ,  H01L29/42312 ,  H01L29/66356 ,  H01L29/7391

Abstract: A microelectronic device includes a P-I-N (p+ region, intrinsic semiconductor, and n+ region) semiconductive body with a first gate and a second gate. The first gate is a gate stack disposed on an upper surface plane, and the second gate accesses the semiconductive body from a second plane that is out of the first plane.

Abstract translation: 微电子器件包括具有第一栅极和第二栅极的P-I-N（p +区域，本征半导体和n +区域）半导体。 第一栅极是设置在上表面平面上的栅极堆叠，并且第二栅极从超出第一平面的第二平面访问半导体本体。

公开(公告)号：US08071983B2

公开(公告)日：2011-12-06

申请号：US12463309

申请日：2009-05-08

Applicant: Justin K. Brask ,  Jack Kavalieros ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau ,  Brian S. Doyle

Inventor： Justin K. Brask ,  Jack Kavalieros ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau ,  Brian S. Doyle

IPC: H01L29/10

CPC classification number: H01L29/7853 ,  H01L21/30608 ,  H01L21/30617 ,  H01L21/3085 ,  H01L21/84 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/78681 ,  H01L29/78684

Abstract: A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.

Abstract translation: 对半导体膜的图案化方法进行说明。 根据本发明的实施例，在具有全局晶体取向的硅膜上形成硬掩模材料，其中半导体膜具有第一晶面和第二晶面，其中第一晶面比第二晶面更致密 并且其中所述硬掩模形成在所述第二晶体平面上。 接下来，将硬掩模和半导体膜图案化成硬掩模覆盖的半导体结构。 然后将覆盖有硬掩模的半导体半导体暴露于具有足够化学强度以蚀刻第二晶面但湿度不足以蚀刻第一晶体面的湿蚀刻工艺。

公开(公告)号：US07973389B2

公开(公告)日：2011-07-05

申请号：US12590562

申请日：2009-11-10

Applicant: Rafael Rios ,  Jack Kavalieros ,  Stephen M. Cea

Inventor： Rafael Rios ,  Jack Kavalieros ,  Stephen M. Cea

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/41

CPC classification number: H01L29/66795 ,  H01L29/785

Abstract: A method of forming an isolated tri-gate semiconductor body comprises patterning a bulk substrate to form a fin structure, depositing an insulating material around the fin structure, recessing the insulating material to expose a portion of the fin structure that will be used for the tri-gate semiconductor body, depositing a nitride cap over the exposed portion of the fin structure to protect the exposed portion of the fin structure, and carrying out a thermal oxidation process to oxidize an unprotected portion of the fin structure below the nitride cap. The oxidized portion of the fin isolates the semiconductor body that is being protected by the nitride cap. The nitride cap may then be removed. The thermal oxidation process may comprise annealing the substrate at a temperature between around 900° C. and around 1100° C. for a time duration between around 0.5 hours and around 3 hours.

Abstract translation: 形成隔离的三栅极半导体器件的方法包括：图案化块状衬底以形成翅片结构，在鳍结构周围沉积绝缘材料，使绝缘材料凹陷以暴露将用于三极管的鳍结构的一部分 - 半导体本体，在所述鳍结构的暴露部分上沉积氮化物帽以保护所述鳍结构的暴露部分，以及执行热氧化工艺以将所述鳍状结构的未受保护的部分氧化在所述氮化物帽下方。 翅片的氧化部分隔离被氮化物盖保护的半导体主体。 然后可以去除氮化物盖。 热氧化过程可以包括在大约900℃和大约1100℃之间的温度下退火约0.5小时至约3小时的时间。

公开(公告)号：US07915642B2

公开(公告)日：2011-03-29

申请号：US12319097

申请日：2008-12-30

Applicant: Ravi Pillarisetty ,  Mantu Hudait ,  Marko Radosavljevic ,  Willy Rachmady ,  Gilbert Dewey ,  Jack Kavalieros

Inventor： Ravi Pillarisetty ,  Mantu Hudait ,  Marko Radosavljevic ,  Willy Rachmady ,  Gilbert Dewey ,  Jack Kavalieros

IPC: H01L29/778

CPC classification number: H01L29/155 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/0653 ,  H01L29/205 ,  H01L29/207 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7831

Abstract: Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed.

Abstract translation: 本文通常描述用于提供包括调制掺杂晶体管的三维互补金属氧化物半导体器件的装置和方法的实施例。 可以描述和要求保护其他实施例。

公开(公告)号：US20100163848A1

公开(公告)日：2010-07-01

申请号：US12347883

申请日：2008-12-31

Applicant: Prashant Majhi ,  Jack Kavalieros ,  Wilman Tsai

Inventor： Prashant Majhi ,  Jack Kavalieros ,  Wilman Tsai

IPC: H01L29/66 ,  H01L29/165 ,  H01L21/20

CPC classification number: H01L29/7782 ,  H01L21/02381 ,  H01L21/02387 ,  H01L21/0245 ,  H01L21/02494 ,  H01L21/02505 ,  H01L21/02532 ,  H01L29/1075

Abstract: Embodiments of the present invention describe a semiconductor device having an buffer structure and methods of fabricating the buffer structure. The buffer structure is formed between a substrate and a quantum well layer to prevent defects in the substrate and quantum well layer due to lattice mismatch. The buffer structure comprises a first buffer layer formed on the substrate, a plurality of blocking members formed on the first buffer layer, and second buffer formed on the plurality of blocking members. The plurality of blocking members prevent the second buffer layer from being deposited directly onto the entire first buffer layer so as to minimize lattice mismatch and prevent defects in the first and second buffer layers.

Abstract translation: 本发明的实施例描述了具有缓冲结构的半导体器件和制造缓冲结构的方法。 缓冲结构形成在衬底和量子阱层之间，以防止由于晶格失配而引起的衬底和量子阱层中的缺陷。 缓冲结构包括形成在基板上的第一缓冲层，形成在第一缓冲层上的多个阻挡构件和形成在多个阻挡构件上的第二缓冲器。 多个阻挡构件防止第二缓冲层直接沉积在整个第一缓冲层上，以便最小化晶格失配并防止第一和第二缓冲层中的缺陷。