Isolated tri-gate transistor fabricated on bulk substrate
    78.
    发明授权
    Isolated tri-gate transistor fabricated on bulk substrate 有权
    在本体衬底上制造的隔离三栅极晶体管

    公开(公告)号:US07973389B2

    公开(公告)日:2011-07-05

    申请号:US12590562

    申请日:2009-11-10

    CPC classification number: H01L29/66795 H01L29/785

    Abstract: A method of forming an isolated tri-gate semiconductor body comprises patterning a bulk substrate to form a fin structure, depositing an insulating material around the fin structure, recessing the insulating material to expose a portion of the fin structure that will be used for the tri-gate semiconductor body, depositing a nitride cap over the exposed portion of the fin structure to protect the exposed portion of the fin structure, and carrying out a thermal oxidation process to oxidize an unprotected portion of the fin structure below the nitride cap. The oxidized portion of the fin isolates the semiconductor body that is being protected by the nitride cap. The nitride cap may then be removed. The thermal oxidation process may comprise annealing the substrate at a temperature between around 900° C. and around 1100° C. for a time duration between around 0.5 hours and around 3 hours.

    Abstract translation: 形成隔离的三栅极半导体器件的方法包括:图案化块状衬底以形成翅片结构,在鳍结构周围沉积绝缘材料,使绝缘材料凹陷以暴露将用于三极管的鳍结构的一部分 - 半导体本体,在所述鳍结构的暴露部分上沉积氮化物帽以保护所述鳍结构的暴露部分,以及执行热氧化工艺以将所述鳍状结构的未受保护的部分氧化在所述氮化物帽下方。 翅片的氧化部分隔离被氮化物盖保护的半导体主体。 然后可以去除氮化物盖。 热氧化过程可以包括在大约900℃和大约1100℃之间的温度下退火约0.5小时至约3小时的时间。

    BUFFER STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHODS OF FABRICATION
    80.
    发明申请
    BUFFER STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHODS OF FABRICATION 有权
    半导体器件的缓冲结构和制造方法

    公开(公告)号:US20100163848A1

    公开(公告)日:2010-07-01

    申请号:US12347883

    申请日:2008-12-31

    Abstract: Embodiments of the present invention describe a semiconductor device having an buffer structure and methods of fabricating the buffer structure. The buffer structure is formed between a substrate and a quantum well layer to prevent defects in the substrate and quantum well layer due to lattice mismatch. The buffer structure comprises a first buffer layer formed on the substrate, a plurality of blocking members formed on the first buffer layer, and second buffer formed on the plurality of blocking members. The plurality of blocking members prevent the second buffer layer from being deposited directly onto the entire first buffer layer so as to minimize lattice mismatch and prevent defects in the first and second buffer layers.

    Abstract translation: 本发明的实施例描述了具有缓冲结构的半导体器件和制造缓冲结构的方法。 缓冲结构形成在衬底和量子阱层之间,以防止由于晶格失配而引起的衬底和量子阱层中的缺陷。 缓冲结构包括形成在基板上的第一缓冲层,形成在第一缓冲层上的多个阻挡构件和形成在多个阻挡构件上的第二缓冲器。 多个阻挡构件防止第二缓冲层直接沉积在整个第一缓冲层上,以便最小化晶格失配并防止第一和第二缓冲层中的缺陷。

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