公开(公告)号：US06459127B1

公开(公告)日：2002-10-01

申请号：US10043793

申请日：2002-01-14

Applicant: Jian-Hsing Lee ,  Kuo-Chio Liu ,  Bing-Lung Liao ,  Jiaw-Ren Shih

Inventor： Jian-Hsing Lee ,  Kuo-Chio Liu ,  Bing-Lung Liao ,  Jiaw-Ren Shih

IPC: H01L2362

CPC classification number: H01L27/0266

Abstract: NMOS transistors for a high voltage process are protected from electrostatic discharge (ESD) by parasitic SCRs, where the two NMOS transistors and the two SCRs are designed to be in a completely symmetrical arrangement so that the currents in the components of the SCRs are completely uniform. This symmetry is achieved by adding a p+ diffusion to the source of one of the NMOS transistors. The added p+ diffusion guarantees that the resistance seen by both SCRs is identical. This insures even current distribution between both SCRs and thereby improves the high voltage characteristics of the ESD device.

Abstract translation: 用于高电压工艺的NMOS晶体管通过寄生SCR防止静电放电（ESD），其中两个NMOS晶体管和两个SCR被设计为完全对称的布置，使得SCR的部件中的电流是完全均匀的 。 该对称性是通过向NMOS晶体管之一的源极添加p +扩散来实现的。 添加的p +扩散保证两个SCR看到的电阻是相同的。 这确保了两个SCR之间的均匀电流分布，从而改善了ESD器件的高电压特性。

公开(公告)号：US06437408B1

公开(公告)日：2002-08-20

申请号：US09904146

申请日：2001-07-13

Applicant: Jiaw-Ren Shih ,  Shui-Hung Shen ,  Jian-Hsing Lee ,  Chrong Jung Lin

Inventor： Jiaw-Ren Shih ,  Shui-Hung Shen ,  Jian-Hsing Lee ,  Chrong Jung Lin

IPC: H01L2100

CPC classification number: H01L21/28123

Abstract: A plasma damage protection cell using floating N/P/N and P/N/P structure, and a method to form the same are disclosed. Floating structures of the protection cell and the floating gates for the MOS devices are formed simultaneously on a semiconductor substrate having shallow trench isolation. The floating structures are implanted separately to form the N/P/N and P/N/P bipolar base, emitter and collector regions while the source/drain of the respective NMOS and PMOS devices are implanted with appropriate sequencing. The floating structures are connected to the substrate with appropriate polarity to provide protection at low leakage current levels and with tunable punch-through voltages.

Abstract translation: 公开了使用浮动N / P / N和P / N / P结构的等离子体损伤保护单元及其形成方法。 保护电池的浮动结构和用于MOS器件的浮置栅极同时形成在具有浅沟槽隔离的半导体衬底上。 分别注入浮动结构以形成N / P / N和P / N / P双极基极，发射极和集电极区域，同时以适当的顺序植入各个NMOS和PMOS器件的源极/漏极。 浮动结构以适当的极性连接到基板，以在低泄漏电流水平和可调穿通电压下提供保护。

公开(公告)号：US06323523B1

公开(公告)日：2001-11-27

申请号：US09494682

申请日：2000-01-31

Applicant: Jian-Hsing Lee ,  Yi-Hsun Wu ,  Shui-Hung Chen ,  Jiaw-Ren Shih

Inventor： Jian-Hsing Lee ,  Yi-Hsun Wu ,  Shui-Hung Chen ,  Jiaw-Ren Shih

IPC: H01L2362

CPC classification number: H01L27/0262 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An ESD protective circuit formed by n-type pull-up transistors and n-type pull-down transistors on a p-type silicon substrate for protecting an internal device circuit is disclosed. In the circuit, a n-well region having a p+ diffusion and a n+ diffusion therein being formed adjacent one drain region of one pull-up transistors, the p+ diffusion and a n+ diffusion, as well as all the drain regions of the pull-up transistors are coupled to a power supply. All the source regions of the pull-up transistors and drain regions of the pull-down transistors are connected to an I/O pad. All the source regions of the pull-down transistors including the p+ guardings are grounded. The gates of all transistors are connected to the internal device circuit so that the internal device circuit will be immunity from the ESD.

Abstract translation: 公开了一种用于保护内部器件电路的p型硅衬底上的n型上拉晶体管和n型下拉晶体管形成的ESD保护电路。 在该电路中，在一个上拉晶体管的一个漏极区附近形成有p +扩散和n +扩散的n阱区，p +扩散和n +扩散以及所述漏极区的所有漏极区， 上拉晶体管耦合到电源。 下拉晶体管的上拉晶体管和漏极区域的所有源极区域都连接到I / O焊盘。 包括p +保护的下拉晶体管的所有源极区域接地。 所有晶体管的栅极连接到内部器件电路，使得内部器件电路将免受ESD的影响。

公开(公告)号：US06277723B1

公开(公告)日：2001-08-21

申请号：US09418030

申请日：1999-10-14

Applicant: Jiaw-Ren Shih ,  Shui-Hung Chen ,  Jian-Hsing Lee ,  Chrong Jung Lin

Inventor： Jiaw-Ren Shih ,  Shui-Hung Chen ,  Jian-Hsing Lee ,  Chrong Jung Lin

IPC: H01L2144

CPC classification number: H01L21/28123

Abstract: A plasma damage protection cell using floating N/P/N and P/N/P structure, and a method to form the same are disclosed. Floating structures of the protection cell and the floating gates for the MOS devices are formed simultaneously on a semiconductor substrate having shallow trench isolation. The floating structures are implanted separately to form the N/P/N and P/N/P bipolar base, emitter and collector regions while the source/drain of the respective NMOS and PMOS devices are implanted with appropriate sequencing. The floating structures are connected to the substrate with appropriate polarity to provide protection at low leakage current levels and with tunable punch-through voltages.

Abstract translation: 公开了使用浮动N / P / N和P / N / P结构的等离子体损伤保护单元及其形成方法。 保护电池的浮动结构和用于MOS器件的浮置栅极同时形成在具有浅沟槽隔离的半导体衬底上。 分别注入浮动结构以形成N / P / N和P / N / P双极基极，发射极和集电极区域，同时以适当的顺序植入各个NMOS和PMOS器件的源极/漏极。 浮动结构以适当的极性连接到基板，以在低泄漏电流水平和可调穿通电压下提供保护。

公开(公告)号：US06246075B1

公开(公告)日：2001-06-12

申请号：US09507883

申请日：2000-02-22

Applicant: Hung-Der Su ,  Jian-Hsing Lee ,  Di-Son Kuo

Inventor： Hung-Der Su ,  Jian-Hsing Lee ,  Di-Son Kuo

IPC: H01L2358

CPC classification number: H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An ensemble of test structures comprising arrays of polysilicon plate MOS capacitors for the measurement of electrical quality of the MOSFET gate insulation is described. The test structures also measure plasma damage to these gate insulators incurred during metal etching and plasma ashing of photoresist. The structures are formed, either on test wafers or in designated areas of wafers containing integrated circuit chips. One of the test structures is designed primarily to minimize plasma damage so that oxide quality, and defect densities may be measured unhampered by interface traps created by plasma exposure. Other structures provide different antenna-to-oxide area ratios, useful for assessing plasma induced oxide damage and breakdown. The current-voltage characteristics of the MOS capacitors are measured by probing the structures on the wafer, thereby providing timely process monitoring capability.

Abstract translation: 描述了包括用于测量MOSFET栅极绝缘的电气质量的多晶硅板MOS电容器阵列的测试结构的集合。 测试结构还测量在金属蚀刻和光致抗蚀剂的等离子体灰化期间引起的这些栅绝缘体的等离子体损伤。 在测试晶片上或在包含集成电路芯片的晶片的指定区域中形成结构。 其中一个测试结构主要设计为最小化等离子体损伤，从而可以通过等离子体曝光产生的界面陷阱来测量氧化物质量和缺陷密度。 其他结构提供不同的天线到氧化物面积比，可用于评估等离子体诱导的氧化物损伤和击穿。 通过探测晶片上的结构来测量MOS电容器的电流 - 电压特性，从而提供及时的过程监控能力。

公开(公告)号：US6122201A

公开(公告)日：2000-09-19

申请号：US421516

申请日：1999-10-20

Applicant: Jian-Hsing Lee ,  Kuo-Reay Peng ,  Shui-Hung Chen ,  Jiaw-Ren Shih

Inventor： Jian-Hsing Lee ,  Kuo-Reay Peng ,  Shui-Hung Chen ,  Jiaw-Ren Shih

IPC: G11C16/16 ,  G11C16/04

CPC classification number: G11C16/16

Abstract: A method to channel erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to channel erase a flash EEPROM cell begins by removing the charge from the floating gate of the flash EEPROM cell. The channel erasing consists of applying a relatively large clipped sinusoidal negative voltage pulse to the control gate of said EEPROM cell and concurrently applying a moderately large positive voltage pulse to a first diffusion region. At the same time a ground reference potential is applied to the semiconductor substrate, while the drain, the source and a second diffusion well are allowed to float.

Abstract translation: 在快速EEPROM的隧道氧化物中捕获电荷的同时消除闪存EEPROM擦除数据的方法，以便在延长编程和擦除周期之后，保持编程阈值电压和擦除阈值电压的适当分离。 通过从闪存EEPROM单元的浮动栅极去除电荷，开始通道擦除闪存EEPROM单元的方法。 通道擦除包括将相对较大的限幅正弦负电压脉冲施加到所述EEPROM单元的控制栅极，同时向第一扩散区域施加适度大的正电压脉冲。 同时，对半导体衬底施加接地参考电位，同时使漏极，源极和第二扩散阱浮动。

公开(公告)号：US6066879A

公开(公告)日：2000-05-23

申请号：US304304

申请日：1999-05-03

Applicant: Jian-Hsing Lee ,  Kuo-Chio Liu

Inventor： Jian-Hsing Lee ,  Kuo-Chio Liu

IPC: H01L27/02 ,  H01L23/62

CPC classification number: H01L27/0262 ,  H01L27/0266 ,  H01L29/87 ,  H01L2924/0002

Abstract: A device layout is disclosed for an ESD device for protecting NMOS or Drain-Extended (DENMOS) high power transistors where the protection device (an SCR) and the NMOS or DENMOS transistors are integrated saving on silicon real estate. The integration is made possible by adding a p.sup.+ diffusion to the n-well (drain) of a high power NMOS (DENMOS) transistor such that the added p.sup.+ diffusion together with the aforementioned n-well and the p-substrate of the silicon wafer create one of the two transistors of the SCR. A low triggering voltage of the SCR is achieved by having the second parasitic npn transistor of the SCR in parallel with the NMOS (DENMOS) transistor by sharing the n-well (collector/drain), p-substrate (base/channel region), and an adjacent n.sup.+ diffusion (emitter/source) in the p-substrate. A high HBM ESD Passing Voltage is obtained by utilizing the tank oxide method of a DENMOS transistor.

Abstract translation: 公开了一种用于ESD器件的器件布局，用于保护NMOS或漏极扩展（DENMOS）高功率晶体管，其中保护器件（SCR）和NMOS或DENMOS晶体管集成在一起，可以节省硅的空间。 通过向高功率NMOS（DENMOS）晶体管的n阱（漏极）添加p +扩散使得加入的p +扩散与上述n阱和硅晶片的p-衬底一起形成，可以实现积分 SCR的两个晶体管之一。 SCR的低触发电压通过使SCR的第二寄生npn晶体管与NMOS（DENMOS）晶体管并联，通过共享n阱（集电极/漏极），p-衬底（基极/沟道区）， 和p-基底中相邻的n +扩散（发射极/源极）。 通过使用DENMOS晶体管的罐式氧化法获得高HBM ESD通过电压。

公开(公告)号：US6049484A

公开(公告)日：2000-04-11

申请号：US150907

申请日：1998-09-10

Applicant: Jian-Hsing Lee ,  Kuo-Reay Peng ,  Juang-Ke Yeh ,  Ming-Chou Ho

Inventor： Jian-Hsing Lee ,  Kuo-Reay Peng ,  Juang-Ke Yeh ,  Ming-Chou Ho

IPC: G11C16/14 ,  G11C16/04

CPC classification number: G11C16/14

Abstract: A method to erase data from a flash EEPROM is disclosed. Electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by erasing the flash EEPROM cell by first applying a high positive voltage pulse to the source of the EEPROM cell. Simultaneously, a ground reference potential is applied to the semiconductor substrate and the control gate. At this same time the drain is floating. Floating the source and drain and applying the ground reference potential to the semiconductor substrate then detraps the flash EEPROM cell. At the same time, a relatively large negative voltage pulse is applied to the control gate.

Abstract translation: 公开了一种从闪存EEPROM擦除数据的方法。 消除了捕获在闪速EEPROM的隧穿氧化物中的电荷，以在扩展编程和擦除周期之后保持编程的阈值电压和擦除的阈值电压的适当分离。 通过首先向EEPROM单元的源施加高正电压脉冲，擦除快闪EEPROM单元开始擦除快闪EEPROM单元的方法。 同时，对半导体衬底和控制栅极施加接地参考电位。 在同一时间，排水沟漂浮。 将源极和漏极浮置并将接地参考电位施加到半导体衬底，然后去除快闪EEPROM单元。 同时，向控制栅极施加相对较大的负电压脉冲。

公开(公告)号：US5726933A

公开(公告)日：1998-03-10

申请号：US857162

申请日：1997-05-15

Applicant: Jian-Hsing Lee ,  Kuo-Reay Peng ,  Juang-Ke Yeh ,  Ming-Chou Ho

Inventor： Jian-Hsing Lee ,  Kuo-Reay Peng ,  Juang-Ke Yeh ,  Ming-Chou Ho

IPC: G11C16/10 ,  G11C16/14 ,  G11C16/06

CPC classification number: G11C16/14 ,  G11C16/10

Abstract: The present invention provides method to erase and program flash EEPROMS devices using a clipped sine waveform (Vg). The clipped sine waveform reduces the tunneling oxide electric field between the floating gate and the source or drain region thereby reducing electron trapping. The method for the erase cycle comprises: applying a positive voltage to a source region; grounding a well region; floating the drain region; and simultaneously applying a negative clipped sine waveform voltage to a control gate during the erase cycle. The program cycle of the invention comprises: applying a voltage to a drain region; grounding a well region; floating a source region; and simultaneously applying a clipped sine waveform voltage to the control gate whereby the clipped sine waveforms reduce the electric field in a tunnel oxide layer which reduces the electron trapping.

Abstract translation: 本发明提供了使用限幅正弦波形（Vg）擦除和编程闪存EEPROMS设备的方法。 限幅正弦波形减少了浮动栅极和源极或漏极区域之间的隧道氧化物电场，从而减少了电子俘获。 擦除周期的方法包括：向源极区域施加正电压; 接地井区; 漂浮漏极区; 并且在擦除周期期间同时向控制栅极施加负的限幅正弦波形电压。 本发明的程序循环包括：向漏区施加电压; 接地井区; 浮动源区; 并且同时向限制栅极施加限幅正弦波形电压，由此限幅正弦波形减少隧道氧化物层中的电场，从而减少电子捕获。

公开(公告)号：US5561387A

公开(公告)日：1996-10-01

申请号：US507532

申请日：1995-07-26

Applicant: Jian-Hsing Lee

Inventor： Jian-Hsing Lee

IPC: G01R31/26 ,  G01R31/22

CPC classification number: G01R31/2621

Abstract: The thickness of the gate insulation layer in an FET has been measured by relating it to its Fowler-Nordheim tunneling field. This Fowler-Nordheim tunneling field is measured in-situ and is non-destructive. Details of the method and apparatus are given.

Abstract translation: 已经通过将其与其Fowler-Nordheim隧道场相关联来测量FET中的栅极绝缘层的厚度。 这个Fowler-Nordheim隧道场是原位测量的，是非破坏性的。 给出方法和装置的细节。