公开(公告)号：US08502713B1

公开(公告)日：2013-08-06

申请号：US13470701

申请日：2012-05-14

Applicant: Jin-Fu Lin

Inventor： Jin-Fu Lin

IPC: H03M1/06

CPC classification number: H03M1/0607 ,  H03M1/0695 ,  H03M1/167 ,  H03M1/44

Abstract: A method for correcting a voltage offset influence of a pipelined analog to digital converter is disclosed, in which the method generates a first stage code and a first output voltage according to a first input voltage, generates a second stage code according to the first output voltage, generates a check code according to the first output voltage, determines a first correction code by referring to the first stage code and the check code, and corrects the first stage code with the first correction code when the first stage code is different from the first correction code.

Abstract translation: 公开了一种用于校正流水线模数转换器的电压偏移影响的方法，其中该方法根据第一输入电压产生第一级代码和第一输出电压，根据第一输出电压产生第二级代码 根据第一输出电压生成检查码，通过参照第一级代码和校验码确定第一校正码，并且当第一级代码与第一级代码不同于第一级代码时，用第一校正码校正第一级代码 校正码。

公开(公告)号：US20130076554A1

公开(公告)日：2013-03-28

申请号：US13240806

申请日：2011-09-22

Applicant: YUAN-KAI CHU ,  Jin-Fu LIN

Inventor： YUAN-KAI CHU ,  Jin-Fu LIN

IPC: H03M1/38 ,  H03M1/12

CPC classification number: H03M1/14

Abstract: A SAR ADC, used for converting an analog input into an N-bit digital output in a conversion phase, includes: three comparators, each two capacitor sub-arrays, coupled to the three comparators respectively, wherein the two capacitor sub-arrays are used for sampling the analog input and providing two inputs for the corresponding comparator; and an SAR logic, coupled to the three comparators and the three capacitor arrays, for, in each conversion sub-phase, coupling two selected capacitors of each capacitor sub-array to a set of determined reference levels, coupling two capacitors, which were selected in a preceding conversion sub-phase, of each capacitor sub-array to a set of adjusted reference levels obtained based on a set of data outputted from the three comparators in a preceding conversion sub-phase, and then generating two bits of the N-bit digital output by encoding a set of data outputted from the three comparators.

Abstract translation: 用于在转换阶段将模拟输入转换成N位数字输出的SAR ADC包括：三个比较器，每两个电容器子阵列分别耦合到三个比较器，其中使用两个电容器子阵列 用于对模拟输入进行采样并为相应的比较器提供两个输入; 以及耦合到三个比较器和三个电容器阵列的SAR逻辑，用于在每个转换子相中，将每个电容器子阵列的两个选定的电容器耦合到一组确定的参考电平，耦合两个选择的电容器 在前一转换子阶段中，将每个电容器子阵列转换成基于在前一转换子相中从三个比较器输出的一组数据而获得的一组调整参考电平，然后产生N位的两位， 通过对从三个比较器输出的一组数据进行编码来进行位数字输出。

公开(公告)号：US08400343B1

公开(公告)日：2013-03-19

申请号：US13276287

申请日：2011-10-18

Applicant: Jin-Fu Lin

Inventor： Jin-Fu Lin

IPC: H03M1/38

CPC classification number: H03M1/14 ,  H03M1/164 ,  H03M1/468

Abstract: A stage of a pipeline analog-to-digital converter (ADC) is provided according to embodiments of the present invention. The stage of the present invention has double-amplifier architecture and uses level-shifting technique to generate a residue of the stage. The amplifiers of the stage are implemented in two different split paths, thereby to generate a relatively coarse amplification result and a relative fine amplification result. The relatively coarse amplification result is used to level-shift the output level of the amplifier. As a result, the stage of the present invention can have a correct residual by using amplifiers of moderate quality.

Abstract translation: 根据本发明的实施例提供了一个流水线模数转换器（ADC）的级。 本发明的阶段具有双放大器架构，并且使用电平转换技术来产生阶段的残留。 级的放大器以两个不同的分离路径实现，从而产生相对粗略的放大结果和相对精细的放大结果。 相对粗略的放大结果用于对放大器的输出电平进行电平移位。 结果，通过使用中等质量的放大器，本发明的阶段可以具有正确的残差。

公开(公告)号：US08344930B2

公开(公告)日：2013-01-01

申请号：US13101127

申请日：2011-05-04

Applicant: Jin-Fu Lin

Inventor： Jin-Fu Lin

IPC: H03M1/12

CPC classification number: H03M1/002 ,  H03M1/468

Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) includes a first capacitor array, a first input capacitor, a first switch module, a second capacitor array, a second input capacitor, a second switch module, a comparator and a SAR controller. The SAR ADC is operated under sampling phases and amplifying phases many times to perform amplifying operations and ADC operations upon input signals to generate digital output data. In addition, because the SAR ADC has both an amplification function and an ADC function, a circuit utilizing the SAR ADC does not require an additional active PGA, and a power consumption of the circuit is decreased.

Abstract translation: 逐次逼近寄存器（SAR）模数转换器（ADC）包括第一电容器阵列，第一输入电容器，第一开关模块，第二电容器阵列，第二输入电容器，第二开关模块，比较器和 一个SAR控制器。 SAR ADC在采样相位和放大阶段多次运行，以对输入信号进行放大操作和ADC操作，以生成数字输出数据。 此外，由于SAR ADC具有放大功能和ADC功能，所以使用SAR ADC的电路不需要额外的有源PGA，电路的功耗也会降低。

公开(公告)号：US20120280846A1

公开(公告)日：2012-11-08

申请号：US13101127

申请日：2011-05-04

Applicant: Jin-Fu Lin

Inventor： Jin-Fu Lin

IPC: H03M1/12

CPC classification number: H03M1/002 ,  H03M1/468

Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) includes a first capacitor array, a first input capacitor, a first switch module, a second capacitor array, a second input capacitor, a second switch module, a comparator and a SAR controller. The SAR ADC is operated under sampling phases and amplifying phases many times to perform amplifying operations and ADC operations upon input signals to generate digital output data. In addition, because the SAR ADC has both an amplification function and an ADC function, a circuit utilizing the SAR ADC does not require an additional active PGA, and a power consumption of the circuit is decreased.

Abstract translation: 逐次逼近寄存器（SAR）模数转换器（ADC）包括第一电容器阵列，第一输入电容器，第一开关模块，第二电容器阵列，第二输入电容器，第二开关模块，比较器和 一个SAR控制器。 SAR ADC在采样相位和放大阶段多次运行，以对输入信号进行放大操作和ADC操作，以生成数字输出数据。 此外，由于SAR ADC具有放大功能和ADC功能，所以使用SAR ADC的电路不需要额外的有源PGA，电路的功耗也会降低。

公开(公告)号：US07924204B2

公开(公告)日：2011-04-12

申请号：US12247186

申请日：2008-10-07

Applicant: Soon-Jyh Chang ,  Jin-Fu Lin ,  Chih-Haur Huang

Inventor： Soon-Jyh Chang ,  Jin-Fu Lin ,  Chih-Haur Huang

IPC: H03M1/38

CPC classification number: H03M1/1225 ,  H03M1/0695 ,  H03M1/162 ,  H03M1/164 ,  H03M1/40 ,  H03M1/44

Abstract: An analog-to-digital converter (ADC) for pipelined ADCs or cyclic ADCs is disclosed. The ADC includes at least one pair of two stages connected in series, and the two stages have different bits of resolution. An amplifier is shared by the pair of two stages such that the two stages operate in an interleaved manner. Accordingly, this stage-resolution scalable opamp-sharing technique is adaptable for pipelined ADC or cyclic ADC, which substantially reduces power consumption and increases operating speed.

Abstract translation: 公开了一种用于流水线ADC或循环ADC的模数转换器（ADC）。 ADC包括串联连接的至少一对两个级，两级具有不同的分辨率。 放大器由一对两个级共享，使得两个级以交错方式操作。 因此，这种阶段分辨率可扩展的运算放大器共享技术适用于流水线ADC或循环ADC，这大大降低了功耗并提高了运行速度。

公开(公告)号：US20100004747A1

公开(公告)日：2010-01-07

申请号：US12168874

申请日：2008-07-07

Applicant: Jin-Fu LIN

Inventor： Jin-Fu LIN

IPC: A61F2/44 ,  A61B17/70 ,  A61B17/04

CPC classification number: A61B17/7059 ,  A61F2/4465 ,  A61F2002/30281 ,  A61F2002/30433 ,  A61F2002/30507 ,  A61F2002/30576 ,  A61F2002/30594 ,  A61F2002/30604 ,  A61F2002/30777 ,  A61F2002/30785 ,  A61F2002/30848 ,  A61F2002/30884 ,  A61F2002/30899 ,  A61F2002/30904 ,  A61F2220/0025 ,  A61F2220/0041 ,  A61F2230/0086 ,  A61F2310/00023

Abstract: A trans-vertebral and intra-vertebral plate and a rectangular cage with a slot for the plate of spinal fixation device are for neutralizing intervertebral movement for the spinal interbody fusion. The rectangular cage with a vertical or oblique slot is inserted into the intervertebral space from the lateral or anterior side of the spinal column and then the plate is inserted through the slot of the cage and hammered into and buried inside two adjacent vertebral bodies, to achieve three-dimensional intervertebral fixation.

Abstract translation: 椎体和脊椎内椎板和脊柱固定装置板的狭槽的矩形笼，用于中和脊椎椎体内融合的椎间运动。 将具有垂直或斜槽的矩形笼从脊柱的侧面或前侧插入到椎间空间中，然后将板插入笼的狭槽中并敲入并埋在两个相邻的椎体内，以实现 三维椎间固定。

公开(公告)号：US07596728B2

公开(公告)日：2009-09-29

申请号：US11870169

申请日：2007-10-10

Applicant: Tsu-Wei Tseng ,  Yu-Jen Huang ,  Chun-Hsien Wu ,  Jin-Fu Li ,  Chien-Yuan Pao

Inventor： Tsu-Wei Tseng ,  Yu-Jen Huang ,  Chun-Hsien Wu ,  Jin-Fu Li ,  Chien-Yuan Pao

IPC: G11C29/00 ,  G01R31/28

CPC classification number: G11C29/44 ,  G11C8/16 ,  G11C29/4401 ,  G11C29/808

Abstract: A built-in self repair (BISR) circuit for a multi-port memory and a method thereof are provided. The circuit includes a test-and-analysis module (TAM) and a defect locating module (DLM) coupled to the TAM. The TAM tests a repairable multi-port memory to generate a fault location and determines whether the test generates a port-specific fault candidate according to the fault location. If a port-specific fault candidate is generated, the DLM generates a defect location based on the fault location and provides the defect location to the TAM so that the TAM can determine how to repair the repairable multi-port memory according to the defect location. If no port-specific fault candidate is generated in the test, the TAM determines how to repair the repairable multi-port memory according to the fault location.

Abstract translation: 提供了一种用于多端口存储器的内置自修复（BISR）电路及其方法。 电路包括测试和分析模块（TAM）和耦合到TAM的缺陷定位模块（DLM）。 TAM测试可修复的多端口内存以产生故障位置，并确定测试是否根据故障位置生成端口特定的故障候选。 如果生成了特定于端口的故障候选，则DLM根据故障位置生成缺陷位置，并向TAM提供缺陷位置，以便TAM根据缺陷位置确定如何修复可修复的多端口存储器。 如果在测试中没有生成端口特定的故障候选，则TAM根据故障位置确定如何修复可修复的多端口存储器。

公开(公告)号：US20090049333A1

公开(公告)日：2009-02-19

申请号：US11837721

申请日：2007-08-13

Applicant: Tsu-Wei Tseng ,  Chih-Chiang Hsu ,  Jin-Fu Li ,  Chien-Yuan Pao

Inventor： Tsu-Wei Tseng ,  Chih-Chiang Hsu ,  Jin-Fu Li ,  Chien-Yuan Pao

IPC: G06F11/22

CPC classification number: G11C29/4401 ,  G11C29/16 ,  G11C29/44 ,  G11C29/70 ,  G11C2029/0401

Abstract: A built-in redundancy analyzer and a redundancy analysis method thereof for a chip having a plurality of repairable memories are provided. The method includes the following steps. First, the identification code of a repairable memory containing a fault (“fault memory” for short) is identified and a parameter is provided according to the identification code. The parameter includes the length of row address, the length of column address, the length of word, the number of redundancy rows, and the number of redundancy columns of the fault memory. Since the parameter of every individual repairable memory is different, the fault location is converted into a general format according to the parameter for easier processing. A redundancy analysis is then performed according to the parameter and the converted fault location, and the analysis result is converted from the general format to the format of the fault memory and output to the fault memory.

Abstract translation: 提供了一种用于具有多个可修复存储器的芯片的内置冗余分析器​​及其冗余分析方法。 该方法包括以下步骤。 首先，识别包含故障的可修复存储器的识别码（简称为“故障存储器”），并根据识别码提供参数。 该参数包括行地址的长度，列地址的长度，字的长度，冗余行的数量以及故障存储器的冗余列数。 由于每个可修复存储器的参数不同，所以根据参数将故障位置转换为一般格式，便于处理。 然后根据参数和转换的故障位置执行冗余分析，并将分析结果从通用格式转换为故障存储器的格式，并输出到故障存储器。

公开(公告)号：US06959991B2

公开(公告)日：2005-11-01

申请号：US10721328

申请日：2003-11-26

Applicant: Francis Ho ,  Minglu Chen ,  Ray Chiu ,  Kevin Kao ,  Jin Fu Sun ,  Bear Tsai ,  Chao Kuan Wu ,  Jason Mar ,  David Li ,  Henry Chien ,  Johnson Yang ,  Alex Chung ,  Yu-Chin Li ,  Chang Te Yang

Inventor： Francis Ho ,  Minglu Chen ,  Ray Chiu ,  Kevin Kao ,  Jin Fu Sun ,  Bear Tsai ,  Chao Kuan Wu ,  Jason Mar ,  David Li ,  Henry Chien ,  Johnson Yang ,  Alex Chung ,  Yu-Chin Li ,  Chang Te Yang

IPC: H04N5/38 ,  H04N5/60 ,  H04N5/74 ,  H04N5/775 ,  G03B21/14

CPC classification number: H04N9/3141 ,  H04N5/38 ,  H04N5/60 ,  H04N5/74 ,  H04N5/775 ,  H04N21/4184 ,  H04N21/42646 ,  H04N21/43637 ,  H04N21/8106

Abstract: An integrated projector comprising a body with a projector circuit internally and a projection lens externally, a card reader installed on the body to read the data inside the memory card, a video interface installed on the body to receive video signals, and a video player that is a DVD player built-in inside the body. Users can read the data in the memory card, watch TV and watch DVD with a single projector without extra wiring.

Abstract translation: 一种集成投影机，其包括内部具有投影仪电路的主体和外部的投影透镜，安装在身体上以读取存储卡内部的数据的读卡器，安装在身体上以接收视频信号的视频接口以及视频播放器， 是内置在身体内的DVD播放机。 用户可以使用单个投影机读取存储卡中的数据，观看电视和观看DVD，无需额外的接线。