公开(公告)号：US08148767B2

公开(公告)日：2012-04-03

申请号：US11709860

申请日：2007-02-23

申请人： Yoon-dong Park ,  June-mo Koo ,  Kyoung-lae Cho

发明人： Yoon-dong Park ,  June-mo Koo ,  Kyoung-lae Cho

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7923

摘要： A semiconductor memory device includes a semiconductor substrate, a control gate electrode recessed in the semiconductor substrate, a storage node layer interposed between a sidewall of the control gate electrode and the semiconductor substrate, a tunneling insulation layer interposed between the storage node layer and the semiconductor substrate, a blocking insulation layer interposed between the storage node layer and the control gate electrode, and first and second channel regions formed around a surface of the semiconductor substrate to at least partially surround the control gate electrode. The semiconductor memory device may include a plurality of control gate electrodes, storage node layers, tunneling insulation layers, blocking insulation layers, and continuous first and second channel regions. A method of fabricating the semiconductor memory device includes etching the semiconductor substrate to form a plurality of holes, forming the tunneling insulation layers, storage node layers, blocking insulation layers, and control gate electrodes.

摘要翻译： 半导体存储器件包括半导体衬底，凹入半导体衬底中的控制栅极电极，插在控制栅电极的侧壁和半导体衬底之间的存储节点层，介于存储节点层和半导体衬底之间的隧道绝缘层 衬底，介于存储节点层和控制栅电极之间的阻挡绝缘层，以及形成在半导体衬底的表面周围以至少部分地围绕控制栅电极的第一和第二沟道区。 半导体存储器件可以包括多个控制栅电极，存储节点层，隧道绝缘层，阻挡绝缘层以及连续的第一和第二沟道区。 制造半导体存储器件的方法包括蚀刻半导体衬底以形成多个孔，形成隧道绝缘层，存储节点层，阻挡绝缘层和控制栅电极。

公开(公告)号：US08112693B2

公开(公告)日：2012-02-07

申请号：US11905734

申请日：2007-10-03

申请人： Jun Jin Kong ,  Seung-Hwan Song ,  Dong Hyuk Chae ,  Kyoung Lae Cho ,  Seung Jae Lee ,  Nam Phil Jo ,  Sung Chung Park ,  Dong Ku Kang

发明人： Jun Jin Kong ,  Seung-Hwan Song ,  Dong Hyuk Chae ,  Kyoung Lae Cho ,  Seung Jae Lee ,  Nam Phil Jo ,  Sung Chung Park ,  Dong Ku Kang

IPC分类号： G11C29/00

CPC分类号： G06F11/1072

摘要： An Error Control Code (ECC) apparatus applied to a memory of a Multi-Level Cell (MLC) method may include: a bypass control signal generator generating a bypass control signal; and an ECC performing unit that may include at least two ECC decoding blocks, determining whether to bypass a portion of the at least two ECC decoding blocks based on the bypass control signal, and/or performing an ECC decoding. In addition or in the alternative, the ECC performing unit may include at least two ECC encoding blocks, determining whether to bypass a portion of the at least two ECC encoding blocks based on the bypass control signal, and/or performing an ECC encoding. An ECC method applied to a memory of a MLC method and a computer-readable recording medium storing a program for implementing an EEC method applied to a memory of a MLC method are also disclose.

摘要翻译： 应用于多电平单元（MLC）方法的存储器的错误控制码（ECC）装置可以包括：旁路控制信号发生器，其生成旁路控制信号; 以及ECC执行单元，其可以包括至少两个ECC解码块，基于旁路控制信号确定是否绕过所述至少两个ECC解码块的一部分，和/或执行ECC解码。 另外或在替代方案中，ECC执行单元可以包括至少两个ECC编码块，基于旁路控制信号确定是否绕过至少两个ECC编码块的一部分，和/或执行ECC编码。 还公开了应用于MLC方法的存储器的ECC方法和存储用于实现应用于MLC方法的存储器的EEC方法的程序的计算机可读记录介质。

公开(公告)号：US20110320689A1

公开(公告)日：2011-12-29

申请号：US13159075

申请日：2011-06-13

申请人： Kyoung Lae Cho ,  Jun-jin Kong ,  Hong-rak Son ,  Seong-hyeong Choi

发明人： Kyoung Lae Cho ,  Jun-jin Kong ,  Hong-rak Son ,  Seong-hyeong Choi

IPC分类号： G06F12/00 ,  G06F12/10

CPC分类号： G06F12/0246 ,  G06F2212/7201

摘要： Methods of operating integrated circuit devices include updating a mapping table with physical address information by reading forward link information from a plurality of spare sectors in a corresponding plurality of pages within a nonvolatile memory device and then writing mapping table information derived from the forward link information into the mapping table. This forward link information may be configured as absolute address information (e.g., next physical address) and/or relative address information (e.g., change in physical address). This updating of the mapping table may include updating a mapping table within a volatile memory, in response to a resumption of power within the integrated circuit device. This resumption of power may follow a power failure during which the contents of the volatile memory are lost.

摘要翻译： 操作集成电路设备的方法包括：通过从非易失性存储器件内的相应多个页面中的多个备用扇区读取前向链路信息，然后将从前向链路信息导出的映射表信息写入到 映射表。 该前向链路信息可以被配置为绝对地址信息（例如，下一个物理地址）和/或相对地址信息（例如，物理地址的改变）。 映射表的这种更新可以包括响应于集成电路设备内的恢复功率而更新易失性存储器内的映射表。 这种恢复电源可能会在易失性存储器的内容丢失的情况下发生电源故障。

公开(公告)号：US08050087B2

公开(公告)日：2011-11-01

申请号：US12071349

申请日：2008-02-20

申请人： Ju-hee Park ,  Jae-woong Hyun ,  Kyoung-lae Cho ,  Yoon-dong Park ,  Seung-hoon Lee ,  Kee-won Kwon

发明人： Ju-hee Park ,  Jae-woong Hyun ,  Kyoung-lae Cho ,  Yoon-dong Park ,  Seung-hoon Lee ,  Kee-won Kwon

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C11/5642 ,  G11C2211/5641 ,  G11C2211/5646

摘要： Provided are a semiconductor device having a block state confirmation cell that may store information indicating the number of data bits written to a plurality of memory cells, a method of reading memory data based on the number of the data bits written, and/or a memory programming method of storing the information indicating the number of the data bits written. The semiconductor device may include one or more memory blocks and a controller. Each of the memory blocks may include a plurality of memory cells each storing data, and a block state confirmation cell storing information indicating the number of data bits written to the memory cells. The controller may read the data bits from the memory blocks based on the number of data bits, which is indicated in the information in the block state confirmation cell.

摘要翻译： 提供了具有块状态确认单元的半导体器件，其可以存储指示写入多个存储器单元的数据位数的信息，基于写入的数据位的数量读取存储器数据的方法和/或存储器 存储指示写入数据位数的信息的编程方法。 半导体器件可以包括一个或多个存储器块和控制器。 每个存储器块可以包括存储数据的多个存储单元，以及存储指示写入存储单元的数据位数的信息的块状态确认单元。 控制器可以基于在块状态确认单元中的信息中指示的数据位数来从存储器块读取数据位。

公开(公告)号：US20110252184A1

公开(公告)日：2011-10-13

申请号：US13082721

申请日：2011-04-08

申请人： Kyoung Lae CHO ,  Donggi LEE ,  Hee Chang CHO ,  Bumseok YU ,  Junjin KONG ,  Hyungjoon PARK

发明人： Kyoung Lae CHO ,  Donggi LEE ,  Hee Chang CHO ,  Bumseok YU ,  Junjin KONG ,  Hyungjoon PARK

IPC分类号： G06F12/02

CPC分类号： G06F12/023 ,  G06F3/0608 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0658 ,  G06F3/0689 ,  G06F12/0246 ,  G06F2212/401 ,  G11B20/00007

摘要： A method of storing data in a storage media is provided which includes sequentially compressing data by a compression unit, and storing the compressed data in the storage media, the compression unit being varied according to a compression characteristic of data to be stored in the storage media.

摘要翻译： 提供了一种在存储介质中存储数据的方法，其包括由压缩单元顺序压缩数据，并将压缩数据存储在存储介质中，压缩单元根据要存储在存储介质中的数据的压缩特性而变化 。

公开(公告)号：US08004886B2

公开(公告)日：2011-08-23

申请号：US12073101

申请日：2008-02-29

申请人： Seung-Hwan Song ,  Kyoung Lae Cho ,  Heeseok Eun ,  Dong Hyuk Chae ,  Jun Jin Kong ,  Sung Chung Park

发明人： Seung-Hwan Song ,  Kyoung Lae Cho ,  Heeseok Eun ,  Dong Hyuk Chae ,  Jun Jin Kong ,  Sung Chung Park

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/3418 ,  G11C2211/5621

摘要： Multi-bit programming apparatuses and/or methods are provided. A multi-bit programming apparatus may comprise: a multi-bit cell array that includes a first multi-bit cell and a second multi-bit cell; a programming unit for programming first data in the first multi-bit cell, and programming second data in the second multi-bit cell; and a verification unit for verifying whether the first data is programmed in the first multi-bit cell using a first verification voltage, and verifying whether the second data is programmed in the second multi-bit cell using a second verification voltage. The multi-bit programming apparatus may generate better threshold voltage distributions in a multi-bit cell memory.

摘要翻译： 提供了多位编程设备和/或方法。 多比特编程装置可以包括：包括第一多比特小区和第二多比特小区的多比特单元阵列; 编程单元，用于对第一多位单元中的第一数据进行编程，以及编程第二多位单元中的第二数据; 以及验证单元，用于使用第一验证电压来验证第一数据是否被编程在第一多位单元中，以及使用第二验证电压来验证第二数据是否被编程在第二多位单元中。 多比特编程装置可以在多比特单元存储器中产生更好的阈值电压分布。

公开(公告)号：US07885107B2

公开(公告)日：2011-02-08

申请号：US12219663

申请日：2008-07-25

申请人： Ju-hee Park ,  Young-moon Kim ,  Yoon-dong Park ,  Seung-hoon Lee ,  Kyoung-lae Cho ,  Sung-jae Byun ,  Seung-hwan Song

发明人： Ju-hee Park ,  Young-moon Kim ,  Yoon-dong Park ,  Seung-hoon Lee ,  Kyoung-lae Cho ,  Sung-jae Byun ,  Seung-hwan Song

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C11/5628 ,  G11C2211/5621 ,  G11C2211/5648

摘要： A method of programming a non-volatile memory cell includes programming a first bit of multi-bit data by setting a threshold voltage of the non-volatile memory cell to a first voltage level within a first of a plurality of threshold voltage distributions. A second bit of the multi-bit data is programmed by setting the threshold voltage to a second voltage level based on a value of the second bit. The second voltage level is the same as the first voltage level if the second bit is a first value and the second voltage level is within a second of the plurality of threshold voltage distributions if the second bit is a second value. A third bit of the multi-bit data is programmed by setting the threshold voltage to a third voltage level based on a value of the third bit.

摘要翻译： 一种编程非易失性存储单元的方法包括通过将非易失性存储单元的阈值电压设置为多个阈值电压分布中的第一个内的第一电压电平来对第一位多位数据进行编程。 通过基于第二位的值将阈值电压设置为第二电压电平来编程多位数据的第二位。 如果第二位是第二值，则第二电压电平与第一电压电平相同，如果第二位是第二值，则第二电压电平在多个阈值电压分布的一秒内。 通过将阈值电压设置为基于第三位的值的第三电压电平来编程多位数据的第三位。

公开(公告)号：US20100303299A1

公开(公告)日：2010-12-02

申请号：US12587988

申请日：2009-10-15

申请人： Kyoung Lae Cho ,  Seung Hoon Lee ,  Dong Ki Min

发明人： Kyoung Lae Cho ,  Seung Hoon Lee ,  Dong Ki Min

IPC分类号： G06K9/00

CPC分类号： G01B11/026 ,  G01S7/4816 ,  G01S17/102 ,  G01S17/46 ,  G01S17/89

摘要： A depth sensor includes a light source, a detector, and a signal processor. The light source transmits a source signal to the target according to a transmit control signal having reference time points. The detector receives a reflected signal from the source signal being reflected from the target. The signal processor generates a plurality of sensed values by measuring respective portions of the reflected signal during respective time periods with different time delays from the reference time points. The signal processor determines a respective delay time for a maximum/minimum of the sensed values for determining the distance of the target.

摘要翻译： 深度传感器包括光源，检测器和信号处理器。 光源根据具有参考时间点的发送控制信号将目标信号发送到目标。 检测器接收来自目标反射的源信号的反射信号。 信号处理器通过在从参考时间点起不同的时间延迟的各个时间段期间测量反射信号的各个部分来产生多个感测值。 信号处理器确定用于确定目标距离的感测值的最大值/最小值的相应延迟时间。

公开(公告)号：US07804726B2

公开(公告)日：2010-09-28

申请号：US12073100

申请日：2008-02-29

申请人： Kyoung Lae Cho ,  Jun Jin Kong ,  Jong Han Kim ,  Seung Hoon Lee ,  Young Hwan Lee ,  Sung-Jae Byun ,  Ju Hee Park

发明人： Kyoung Lae Cho ,  Jun Jin Kong ,  Jong Han Kim ,  Seung Hoon Lee ,  Young Hwan Lee ,  Sung-Jae Byun ,  Ju Hee Park

IPC分类号： G11C7/22

CPC分类号： G11C11/5628 ,  G11C2211/5647

摘要： Multi-bit programming apparatuses and methods are provided. A multi-bit programming apparatus includes a page buffer configured to store first data of the page programming operation, an input control unit configured to determine whether to invert the first data based on a number of bits having a first value and a number of bits having a second value. The input control unit is further configured to invert the first data to generate second data if the number of bits having a first value is greater than the number of bits having a second value and store the second data in the page buffer. The multi-bit programming apparatus further includes a page programming unit configured to program the second data stored in the page buffer in at least one multi-bit cell.

摘要翻译： 提供了多位编程设备和方法。 一种多位编程装置，包括：页缓冲器，被配置为存储页编程操作的第一数据;输入控制单元，被配置为基于具有第一值的比特数和具有多个比特的比特数来确定是否反转第一数据 第二个值。 输入控制单元还被配置为如果具有第一值的比特数大于具有第二值的比特数，并且将第二数据存储在页面缓冲器中，则反转第一数据以产生第二数据。 该多位编程装置还包括：页面编程单元，被配置为在至少一个多位单元中对存储在页缓冲器中的第二数据进行编程。

公开(公告)号：US07764543B2

公开(公告)日：2010-07-27

申请号：US12219264

申请日：2008-07-18

申请人： Kyoung Lae Cho ,  Dong Hun Yu ,  Jun Jin Kong ,  Seung-Hwan Song ,  Yoon Dong Park ,  Jong Han Kim ,  Young Hwan Lee

发明人： Kyoung Lae Cho ,  Dong Hun Yu ,  Jun Jin Kong ,  Seung-Hwan Song ,  Yoon Dong Park ,  Jong Han Kim ,  Young Hwan Lee

IPC分类号： G11C16/00

CPC分类号： G11C16/34 ,  G11C11/5642 ,  G11C2211/5634

摘要： A memory device and a method of reading multi-bit data stored in a multi-bit cell array may be provided. The memory device may include a multi-bit cell array including a least one memory page with each memory page having a plurality of multi-bit cells, and a determination unit to divide the plurality of multi-bit cells into a first group and second group. The first group may include multi-bit cells with a threshold voltage higher than a reference voltage. The second group may include multi-bit cells with a threshold voltage lower than the reference voltage. The determination unit may sequentially update the first group and second group while changing the reference voltage.

摘要翻译： 可以提供存储器件和读取存储在多位单元阵列中的多位数据的方法。 存储器件可以包括多比特单元阵列，其包括至少一个存储器页，每个存储器页具有多个多位单元，以及确定单元，用于将多个多位单元划分成第一组和第二组 。 第一组可以包括具有高于参考电压的阈值电压的多位单元。 第二组可以包括阈值电压低于参考电压的多位单元。 确定单元可以在改变参考电压的同时顺序地更新第一组和第二组。