公开(公告)号：US07949794B2

公开(公告)日：2011-05-24

申请号：US11592341

申请日：2006-11-02

Applicant: Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Fallk ,  Avi (Abraham) Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Ellezer Weissmann ,  Doron Shamia

Inventor： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Fallk ,  Avi (Abraham) Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Ellezer Weissmann ,  Doron Shamia

IPC: G06F3/00 ,  G06F13/14

CPC classification number: G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

Abstract: A method and apparatus for enhancing /extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract translation: 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

公开(公告)号：US07849252B2

公开(公告)日：2010-12-07

申请号：US12156409

申请日：2008-05-30

Applicant: Mahesh Wagh ,  Jasmin Ajanovic

Inventor： Mahesh Wagh ,  Jasmin Ajanovic

IPC: G06F13/00

CPC classification number: H04L69/22

Abstract: In one embodiment, the present invention includes a method for generating a prefix header with an opcode field and a prefix specific field for a first packet to be transmitted from a transmitter, and transmitting the packet from the transmitter with the prefix header, which is followed by a header. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于产生具有操作码字段的前缀报头和用于要从发送器发送的第一分组的前缀特定字段的方法，并且从发送器发送具有跟随的前缀报头的分组 通过标题 描述和要求保护其他实施例。

公开(公告)号：US20090249098A1

公开(公告)日：2009-10-01

申请号：US12079185

申请日：2008-03-25

Applicant: Woojong Han ,  Madhu Athreya ,  Ken Shoemaker ,  Arvind Mandhani ,  Mahesh Wagh ,  Ticky Thakkar

Inventor： Woojong Han ,  Madhu Athreya ,  Ken Shoemaker ,  Arvind Mandhani ,  Mahesh Wagh ,  Ticky Thakkar

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3203 ,  G06F1/3243 ,  Y02D10/152

Abstract: In one embodiment, the present invention includes a method for sending a first link handshake signal between a first subsystem and a power management unit (PMU) of a system on a chip (SoC) to request entry into a power saving state for the first subsystem, sending a second link handshake signal between the first subsystem and the PMU to acknowledge the request, and placing the first subsystem into the power saving state without further signaling between the PMU and the first subsystem. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于在芯片上的系统（SoC）的第一子系统和功率管理单元（PMU）之间发送第一链路握手信号以请求进入第一子系统的省电状态的方法 在所述第一子系统和所述PMU之间发送第二链路握手信号以确认所述请求，以及将所述第一子系统置于省电状态，而不在所述PMU与所述第一子系统之间进一步发信号。 描述和要求保护其他实施例。

公开(公告)号：US20090185580A1

公开(公告)日：2009-07-23

申请号：US12009970

申请日：2008-01-23

Applicant: Mahesh Wagh

Inventor： Mahesh Wagh

IPC: H04J3/24 ,  H04J3/16

CPC classification number: G06F13/385 ,  G06F13/4269 ,  H04L12/12 ,  Y02D50/30 ,  Y02D50/40

Abstract: In one embodiment, the present invention includes a method for transmitting a packet from a transmitter to a receiver along an interconnect and terminating transmission of the packet at a packet disconnect boundary, which has a length less than a payload length of the packet. After such termination, another packet such as a higher priority packet can be transmitted, or a remainder of the original packet may be transmitted as a separate packet. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于沿着互连从发射机向接收机发送分组的方法，并且在分组断开边界处终止分组的传输，分组断开边界的长度小于分组的有效载荷长度。 在这种终止之后，可以发送诸如较高优先级分组的另一分组，或者原始分组的剩余部分可以作为单独分组发送。 描述和要求保护其他实施例。

公开(公告)号：US20080109565A1

公开(公告)日：2008-05-08

申请号：US11592341

申请日：2006-11-02

Applicant: Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Fallk ,  Avi Arraham Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Ellezer Weissmann ,  Doron Shamia

Inventor： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Fallk ,  Avi Arraham Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Ellezer Weissmann ,  Doron Shamia

IPC: G06F3/01

CPC classification number: G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

Abstract: A method and apparatus for enhancing /extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract translation: 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

公开(公告)号：US20210112132A1

公开(公告)日：2021-04-15

申请号：US17128648

申请日：2020-12-21

Applicant: NITISH PALIWAL ,  PEEYUSH PUROHIT ,  SWADESH CHOUDHARY ,  MANJULA PEDDIREDDY ,  MAHESH NATU ,  MAHESH WAGH

Inventor： NITISH PALIWAL ,  PEEYUSH PUROHIT ,  SWADESH CHOUDHARY ,  MANJULA PEDDIREDDY ,  MAHESH NATU ,  MAHESH WAGH

IPC: H04L29/08 ,  H04L12/741 ,  H04L12/863

Abstract: In one embodiment, an apparatus includes: a transaction layer circuit to output transaction layer information; and a link layer circuit coupled to the transaction layer circuit, the link layer circuit to receive and process the transaction layer information and to output link layer information to a physical circuit. The link layer circuit may include a first selection circuit to receive and direct cache memory protocol traffic to a selected one of a first logical port and a second logical port. Other embodiments are described and claimed.

公开(公告)号：US09086966B2

公开(公告)日：2015-07-21

申请号：US13840394

申请日：2013-03-15

Applicant: Mahesh Wagh ,  Su Wei Lim

Inventor： Mahesh Wagh ,  Su Wei Lim

IPC: G06F11/07 ,  G06F13/42 ,  G06F1/32

CPC classification number: G06F11/0757 ,  G06F1/3293 ,  G06F11/0745 ,  G06F13/4295 ,  Y02D10/14 ,  Y02D10/151

Abstract: Systems, apparatuses, and method for handling timeouts in a link state training sequence are described. All modules of a port undergoing link state training placed into an intermediate state prior to entry into the lowest power state.

Abstract translation: 描述了用于处理链路状态训练序列中的超时的系统，装置和方法。 正在进行链路状态训练的端口的所有模块在进入最低功率状态之前置于中间状态。

公开(公告)号：US20140281639A1

公开(公告)日：2014-09-18

申请号：US13838220

申请日：2013-03-15

Applicant: Mahesh Wagh ,  Lily Pao Looi

Inventor： Mahesh Wagh ,  Lily Pao Looi

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/325 ,  G06F1/3275 ,  G06F1/3278 ,  G06F1/3287 ,  G06F9/4418 ,  G06F13/4265 ,  G06F13/4282 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/171 ,  Y02D10/44

Abstract: Methods and apparatus relating to device power management state transition latency advertisement for faster boot time are described. In some embodiments, a storage unit stores a value corresponding to a requisite transition delay period for a first agent to exit from a low power consumption state. The first agent writes the value to the storage unit and a second agent waits for the requisite transition delay period (after the first agent initiates its exit from the low power consumption state) before the second agent attempts to communicate with the first agent via a link. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了与设备电源管理状态转换延迟广告相关的方法和装置，用于更快的启动时间。 在一些实施例中，存储单元存储对应于第一代理从低功耗状态退出的必要的转换延迟周期的值。 第一代理人将该值写入存储单元，并且第二代理程序在第二代理程序尝试通过链路与第一代理进行通信之前，等待必要的转换延迟周期（在第一代理程序从低功耗状态退出之后） 。 还公开并要求保护其他实施例。

公开(公告)号：US20140269471A1

公开(公告)日：2014-09-18

申请号：US13840172

申请日：2013-03-15

Applicant: Mahesh Wagh ,  Su Wei Lim

Inventor： Mahesh Wagh ,  Su Wei Lim

IPC: H04W52/02

CPC classification number: G06F1/3287 ,  G06F1/3253 ,  G06F1/3278 ,  G06F9/4418 ,  G06F13/4295 ,  H04W52/0203 ,  Y02D10/151 ,  Y02D10/157 ,  Y02D70/1222 ,  Y02D70/1226 ,  Y02D70/1242 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/164 ,  Y02D70/166

Abstract: Systems, apparatuses, and method for synchronizing port entry into a lowest power state are described. All logic of a port placed into an intermediate state prior to entry into the lowest power state.

Abstract translation: 描述用于将端口条目同步到最低功率状态的系统，装置和方法。 在进入最低功率状态之前，端口的所有逻辑被置于中间状态。

公开(公告)号：US20140237154A1

公开(公告)日：2014-08-21

申请号：US14261934

申请日：2014-04-25

Applicant: Arvind Mandhani ,  Woojong Han ,  Ken Shoemaker ,  Madhu Athreya ,  Mahesh Wagh ,  Shreekant S. Thakkar

Inventor： Arvind Mandhani ,  Woojong Han ,  Ken Shoemaker ,  Madhu Athreya ,  Mahesh Wagh ,  Shreekant S. Thakkar

IPC: G06F13/40

CPC classification number: G06F13/4022 ,  G06F13/4027 ,  G06F13/404 ,  G06F13/4045 ,  G06F13/42

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有根据个人计算机（PC）协议和第二协议进行通信的适配器的装置。 耦合到适配器的第一接口是对从适配器的上游接收的事务执行地址转换和排序。 第一个接口依次耦合到异构资源，每个资源包括知识产权（IP）核心和垫片，其中垫片将为IP核实现PC协议的头部，以使其能够并入设备中而无需 修改。 描述和要求保护其他实施例。