Abstract:
In one embodiment, the present invention includes a method for associating a first priority indicator with data stored in a first entry of a shared cache memory by a core to indicate a priority level of a first thread, and associating a second priority indicator with data stored in a second entry of the shared cache memory by a graphics engine to indicate a priority level of a second thread. Other embodiments are described and claimed.
Abstract:
A method and apparatus for is herein described providing priority aware and consumption guided dynamic probabilistic allocation for a cache memory. Utilization of a sample size of a cache memory is measured for each priority level of a computer system. Allocation probabilities for each priority level are updated based on the measured consumption/utilization, i.e. allocation is reduced for priority levels consuming too much of the cache and allocation is increased for priority levels consuming too little of the cache. In response to an allocation request, it is assigned a priority level. An allocation probability associated with the priority level is compared with a randomly generated number. If the number is less than the allocation probability, then a fill to the cache is performed normally. In contrast, a spatially or temporally limited fill is performed if the random number is greater than the allocation probability.
Abstract:
In one embodiment, a method provides capturing resource monitoring information for a plurality of applications; accessing the resource monitoring information; and scheduling at least one of the plurality of applications on a selected processing core of a plurality of processing cores based, at least in part, on the resource monitoring information.
Abstract:
In one embodiment, the present invention includes a method for maintaining data in a first level cache non-inclusively with data in a second level cache coupled to the first level cache. At the same time, at least a portion of directory information associated with the data in the first level cache may be maintained inclusively with a directory portion of the second level cache. Other embodiments are described and claimed.
Abstract:
Embodiments of apparatuses, methods, and systems for exposing system topology to an execution environment are disclosed. In one embodiment, an apparatus includes execution cores and resources on a single integrated circuit, and topology logic. The topology logic is to populate a data structure with information regarding a relationship between the execution cores and the resources.
Abstract:
Various embodiments for dynamically generating an advertisement in a video stream are disclosed. In one embodiment, video stream content associated with a video stream for a user device is received. Video analytics data is obtained for the video stream content, which indicates a scene recognized in the video stream content. An advertisement to be generated and inserted into the video stream content is then selected based on the scene recognized in the video stream content, and an advertisement template for generating the selected advertisement is obtained. Video advertisement content corresponding to the advertisement is then generated based on the advertisement template and the video analytics data. The video advertisement content is then inserted into the video stream content, and the modified video stream content is transmitted to the user device.
Abstract:
Methods and systems of recognizing images may include an apparatus having a hardware module with logic to, for a plurality of vectors in an image, determine a first intermediate computation based on even pixels of an image vector, and determine a second intermediate computation based on odd pixels of an image vector. The logic can also combine the first and second intermediate computations into a Hessian matrix computation.
Abstract:
In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
Abstract:
In embodiments, apparatuses, methods and storage media (transitory and non-transitory) are described that are associated with end-to-end datacenter performance control. In various embodiments, an apparatus for computing may receive a datacenter performance target, determine an end-to-end datacenter performance level based at least in part on quality of service data collected from a plurality of nodes, and send a mitigation command based at least in part on a result of a comparison of the end-to-end datacenter performance level determined to the datacenter performance target. In various embodiments, the apparatus for computing may include one or more processors, a memory, a datacenter performance monitor to receive a datacenter performance target corresponding to a service level agreement, and a mitigation module to send a mitigation command based at least in part on a result of a comparison of an end-to-end datacenter performance level to a datacenter performance target.
Abstract:
A method and apparatus for throttling power and/or performance of processing elements based on a priority of software entities is herein described. Priority aware power management logic receives priority levels of software entities and modifies operating points of processing elements associated with the software entities accordingly. Therefore, in a power savings mode, processing elements executing low priority applications/tasks are reduced to a lower operating point, i.e. lower voltage, lower frequency, throttled instruction issue, throttled memory accesses, and/or less access to shared resources. In addition, utilization logic potentially trackes utilization of a resource per priority level, which allows the power manager to determine operating points based on the effect of each priority level on each other from the perspective of the resources themselves. Moreover, a software entity itself may assign operating points, which the power manager enforces.