PRIORITY AWARE SELECTIVE CACHE ALLOCATION
    72.
    发明申请
    PRIORITY AWARE SELECTIVE CACHE ALLOCATION 有权
    优先注意选择性高速缓存分配

    公开(公告)号:US20090172315A1

    公开(公告)日:2009-07-02

    申请号:US11965131

    申请日:2007-12-27

    CPC classification number: G06F12/126 G06F9/5016 G06F12/0888

    Abstract: A method and apparatus for is herein described providing priority aware and consumption guided dynamic probabilistic allocation for a cache memory. Utilization of a sample size of a cache memory is measured for each priority level of a computer system. Allocation probabilities for each priority level are updated based on the measured consumption/utilization, i.e. allocation is reduced for priority levels consuming too much of the cache and allocation is increased for priority levels consuming too little of the cache. In response to an allocation request, it is assigned a priority level. An allocation probability associated with the priority level is compared with a randomly generated number. If the number is less than the allocation probability, then a fill to the cache is performed normally. In contrast, a spatially or temporally limited fill is performed if the random number is greater than the allocation probability.

    Abstract translation: 本文描述了提供高速缓冲存储器的优先级感知和消耗引导的动态概率分配的方法和装置。 针对计算机系统的每个优先级测量利用高速缓冲存储器的样本大小。 基于所测量的消耗/利用率来更新每个优先级的分配概率,即对于消耗太多高速缓存的优先级降低了分配,并且对于消耗太多缓存的优先级来说,分配增加。 响应于分配请求,它被分配优先级。 将与优先级相关联的分配概率与随机生成的数字进行比较。 如果该数量小于分配概率,则正常地执行对高速缓存的填充。 相比之下,如果随机数大于分配概率,则执行空间或时间有限的填充。

    Selectively inclusive cache architecture
    74.
    发明授权
    Selectively inclusive cache architecture 有权
    选择性包容性缓存架构

    公开(公告)号:US07552288B2

    公开(公告)日:2009-06-23

    申请号:US11503777

    申请日:2006-08-14

    CPC classification number: G06F12/0811 G06F12/0831

    Abstract: In one embodiment, the present invention includes a method for maintaining data in a first level cache non-inclusively with data in a second level cache coupled to the first level cache. At the same time, at least a portion of directory information associated with the data in the first level cache may be maintained inclusively with a directory portion of the second level cache. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中,本发明包括一种用于在与第一级高速缓存耦合的第二级高速缓存中的数据非包含地维护第一级高速缓存中的数据的方法。 同时,可以与第二级高速缓存的目录部分一起保持与第一级高速缓存中的数据相关联的目录信息的至少一部分。 描述和要求保护其他实施例。

    END-TO-END DATACENTER PERFORMANCE CONTROL
    79.
    发明申请
    END-TO-END DATACENTER PERFORMANCE CONTROL 有权
    端到端数字表现控制

    公开(公告)号:US20160182345A1

    公开(公告)日:2016-06-23

    申请号:US14581595

    申请日:2014-12-23

    Abstract: In embodiments, apparatuses, methods and storage media (transitory and non-transitory) are described that are associated with end-to-end datacenter performance control. In various embodiments, an apparatus for computing may receive a datacenter performance target, determine an end-to-end datacenter performance level based at least in part on quality of service data collected from a plurality of nodes, and send a mitigation command based at least in part on a result of a comparison of the end-to-end datacenter performance level determined to the datacenter performance target. In various embodiments, the apparatus for computing may include one or more processors, a memory, a datacenter performance monitor to receive a datacenter performance target corresponding to a service level agreement, and a mitigation module to send a mitigation command based at least in part on a result of a comparison of an end-to-end datacenter performance level to a datacenter performance target.

    Abstract translation: 在实施例中,描述了与端对端数据中心性能控制相关联的装置,方法和存储介质(暂时性和非暂时性)。 在各种实施例中,用于计算的装置可以接收数据中心性能目标,至少部分地基于从多个节点收集的服务质量数据来确定端对端数据中心性能级别,并且至少基于从多个节点收集的服务数据发送缓解命令 部分原因是比较确定数据中心性能目标的端对端数据中心性能级别。 在各种实施例中,用于计算的装置可以包括一个或多个处理器,存储器,用于接收与服务水平协议相对应的数据中心性能目标的数据中心性能监视器,以及缓解模块,用于至少部分地基于 这是将端到端数据中心性能级别与数据中心性能目标进行比较的结果。

    Priority based throttling for power/performance quality of service
    80.
    发明授权
    Priority based throttling for power/performance quality of service 有权
    基于优先级的电源/性能质量服务节制

    公开(公告)号:US08799902B2

    公开(公告)日:2014-08-05

    申请号:US11786019

    申请日:2007-04-09

    Abstract: A method and apparatus for throttling power and/or performance of processing elements based on a priority of software entities is herein described. Priority aware power management logic receives priority levels of software entities and modifies operating points of processing elements associated with the software entities accordingly. Therefore, in a power savings mode, processing elements executing low priority applications/tasks are reduced to a lower operating point, i.e. lower voltage, lower frequency, throttled instruction issue, throttled memory accesses, and/or less access to shared resources. In addition, utilization logic potentially trackes utilization of a resource per priority level, which allows the power manager to determine operating points based on the effect of each priority level on each other from the perspective of the resources themselves. Moreover, a software entity itself may assign operating points, which the power manager enforces.

    Abstract translation: 这里描述了一种基于软件实体的优先级来节制处理元件的功率和/或性能的方法和装置。 优先级感知功率管理逻辑接收软件实体的优先级,并相应地修改与软件实体相关联的处理元件的工作点。 因此,在省电模式中,执行低优先级应用/任务的处理元件被降低到较低的工作点,即较低的电压,较低的频率,节流的指令问题,节流的存储器访问和/或较少的对共享资源的访问。 此外,利用逻辑潜在地追踪每个优先级别的资源的利用率,这允许电力管理者从资源本身的角度基于每个优先级的影响来确定工作点。 此外,软件实体本身可以分配功率管理器执行的操作点。

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