公开(公告)号：US20120043585A1

公开(公告)日：2012-02-23

申请号：US12860977

申请日：2010-08-23

Applicant: Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin

Inventor： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin

IPC: H01L29/78 ,  H01L21/335 ,  H01L29/772

CPC classification number: H01L29/78 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4236 ,  H01L29/66621

Abstract: A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region.

公开(公告)号：US20120007183A1

公开(公告)日：2012-01-12

申请号：US12832829

申请日：2010-07-08

Applicant: Josephine B. Chang ,  Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin

Inventor： Josephine B. Chang ,  Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin

IPC: H01L29/78 ,  H01L21/20

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L2029/7858

Abstract: A multi-gate transistor having a plurality of sidewall contacts and a fabrication method that includes forming a semiconductor fin on a semiconductor substrate and etching a trench within the semiconductor fin, depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench; and forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer. The method further includes removing exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer, forming a high-k material liner along sidewalls of the channel region in the semiconductor fin, forming a metal gate stack within the etched trench, and forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer.

Abstract translation: 一种具有多个侧壁触点的多栅极晶体管及其制造方法，包括在半导体衬底上形成半导体鳍片并蚀刻半导体鳍片内的沟槽，在蚀刻沟槽内沉积氧化物材料，并蚀刻氧化物材料以形成 沿着蚀刻沟槽内的暴露壁的虚拟氧化物层; 以及沿所述虚拟氧化物层的垂直侧壁形成间隔电介质层。 该方法还包括去除半导体鳍片中的沟道区域中的暴露的虚拟氧化物层并且在间隔物电介质层下方形成沿着半导体鳍片中的沟道区域的侧壁形成高k材料衬垫，在蚀刻 沟槽，并且在半导体鳍片内沿虚拟氧化物层的相邻侧壁形成多个侧壁接触。

公开(公告)号：US20110121370A1

公开(公告)日：2011-05-26

申请号：US12625827

申请日：2009-11-25

Applicant: Dechao Guo ,  Shu-Jen Han ,  Pranita Kulkarni ,  Philip J. Oldiges

Inventor： Dechao Guo ,  Shu-Jen Han ,  Pranita Kulkarni ,  Philip J. Oldiges

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/1054 ,  H01L29/517 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78687

Abstract: A method of fabricating an embedded stressor within a semiconductor structure and a semiconductor structure including the embedded stressor includes forming forming a dummy gate stack over a substrate of stressor material, anistropically etching sidewall portions of the substrate subjacent to the dummy gate stack to form the embedded stressor having angled sidewall portions, forming conductive material onto the angled sidewall portions of the embedded stressor, removing the dummy gate stack, planarizing the conductive material, and forming a gate stack on the conductive material.

Abstract translation: 一种在半导体结构内制造嵌入式应力器的方法以及包括所述嵌入式应力器的半导体结构的方法包括在所述应力源材料的衬底上形成形成虚拟栅极叠层的方法，将所述衬底的与所述虚拟栅极叠层相邻的衬底的侧壁部分， 应力器具有成角度的侧壁部分，将导电材料形成在嵌入式应力源的成角度的侧壁部分上，去除虚拟栅极堆叠，平坦化导电材料，以及在导电材料上形成栅极叠层。

公开(公告)号：US07939338B2

公开(公告)日：2011-05-10

申请号：US11128105

申请日：2005-05-11

Applicant: Shan X. Wang ,  Shu-Jen Han

Inventor： Shan X. Wang ,  Shu-Jen Han

IPC: G01R33/00

CPC classification number: G01R33/09 ,  B82Y25/00 ,  G01N33/5438 ,  G01R33/093 ,  G01R33/12 ,  G01R33/1269 ,  Y10T436/13

Abstract: A magnetic sensor array including magnetoresistive sensor elements having outputs combined by frequency division multiplexing (FDM) is provided. Each sensor element provides an input to a mixer which provides a distinct frequency shift. Preferably, time division multiplexing is also used to combine sensor element outputs. Each sensor element is typically in proximity to a corresponding sample. The sensor elements are preferably subarrays having row and column addressable sensor element pixels. This arrangement provides multiple sensor pixels for each sample under test. Multiplexing of sensor element outputs advantageously reduces readout time. A modulated external magnetic field is preferably applied during operation, to reduce the effect of 1/f noise on the sensor element signals. The effect of electromagnetic interference (EMI) induced by the magnetic field on sensor element signals is advantageously reduced by the mixing required for FDM.

Abstract translation: 提供了包括具有通过频分复用（FDM）组合的输出的磁阻传感器元件的磁传感器阵列。 每个传感器元件为混频器提供输入，该混频器提供不同的频移。 优选地，时分复用也用于组合传感器元件输出。 每个传感器元件通常接近相应的样品。 传感器元件优选地是具有行和列可寻址传感器元件像素的子阵列。 这种布置为每个待测样品提供了多个传感器像素。 传感器元件输出的多路复用有利于减少读出时间。 在操作期间优选地施加调制的外部磁场，以减少1 / f噪声对传感器元件信号的影响。 通过FDM所需的混合有利地减少了由磁场引起的电磁干扰（EMI）对传感器元件信号的影响。

公开(公告)号：US09893212B2

公开(公告)日：2018-02-13

申请号：US13291596

申请日：2011-11-08

Applicant: Zhihong Chen ,  Shu-Jen Han ,  Siyuranga O. Koswatta ,  Alberto Valdes Garcia

Inventor： Zhihong Chen ,  Shu-Jen Han ,  Siyuranga O. Koswatta ,  Alberto Valdes Garcia

IPC: H01L29/93 ,  H01L49/02 ,  B82Y10/00 ,  H01L29/16 ,  B82Y40/00

CPC classification number: H01L29/93 ,  B82Y10/00 ,  B82Y40/00 ,  H01L28/40 ,  H01L29/1606

Abstract: A plate varactor includes a dielectric substrate and a first electrode embedded in a surface of the substrate. A capacitor dielectric layer is disposed over the first electrode, and a layer of graphene is formed over the dielectric layer to contribute a quantum capacitance component to the dielectric layer. An upper electrode is formed on the layer of graphene. Other embodiments and methods for fabrication are also included.

公开(公告)号：US09142660B2

公开(公告)日：2015-09-22

申请号：US13611113

申请日：2012-09-12

Applicant: Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

Inventor： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L21/823487 ,  H01L21/823885 ,  H01L29/4983 ,  H01L29/66666 ,  H01L29/7827

Abstract: A transistor structure is formed to include a substrate and, overlying the substrate, a source; a drain; and a channel disposed vertically between the source and the drain. The channel is coupled to a gate conductor that surrounds the channel via a layer of gate dielectric material that surrounds the channel. The gate conductor is composed of a first electrically conductive material having a first work function that surrounds a first portion of a length of the channel and a second electrically conductive material having a second work function that surrounds a second portion of the length of the channel. A method to fabricate the transistor structure is also disclosed. The transistor structure can be characterized as being a vertical field effect transistor having an asymmetric gate.

Abstract translation: 晶体管结构被形成为包括衬底和覆盖衬底的源极; 排水 以及垂直设置在源极和漏极之间的通道。 通道耦合到栅极导体，该栅极导体通过围绕该沟道的栅极电介质材料层围绕该沟道。 栅极导体由具有围绕通道长度的第一部分的第一功函数的第一导电材料和具有围绕通道长度的第二部分的第二功函数的第二导电材料组成。 还公开了制造晶体管结构的方法。 晶体管结构可以表征为具有非对称栅极的垂直场效应晶体管。

公开(公告)号：US09041057B2

公开(公告)日：2015-05-26

申请号：US13551164

申请日：2012-07-17

Applicant: Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin

Inventor： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4236 ,  H01L29/66621

Abstract: A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region.

Abstract translation: 场效应晶体管器件包括衬底，设置在衬底上的硅锗（SiGe）层，衬在由衬底和硅锗层限定的空腔的表面上的栅介质层，栅极介电层上的金属栅极材料， 填充空腔的金属栅极材料，源极区域和漏极区域。

公开(公告)号：US08916405B2

公开(公告)日：2014-12-23

申请号：US13270362

申请日：2011-10-11

Applicant: Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

Inventor： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

IPC: H01L21/00 ,  H01L33/26 ,  H01L33/00

CPC classification number: H01L33/0041 ,  H01L33/26 ,  H01L33/34 ,  H01L33/40 ,  H01L51/0048 ,  H01L51/5203 ,  H01L51/5296

Abstract: Carbon-based light emitting diodes (LEDs) and techniques for the fabrication thereof are provided. In one aspect, a LED is provided. The LED includes a substrate; an insulator layer on the substrate; a first bottom gate and a second bottom gate embedded in the insulator layer; a gate dielectric on the first bottom gate and the second bottom gate; a carbon material on the gate dielectric over the first bottom gate and the second bottom gate, wherein the carbon material serves as a channel region of the LED; and metal source and drain contacts to the carbon material.

Abstract translation: 提供了碳基发光二极管（LED）及其制造技术。 一方面，提供一种LED。 LED包括基板; 衬底上的绝缘体层; 嵌入在绝缘体层中的第一底栅极和第二底栅极; 第一底栅极和第二底栅极上的栅极电介质; 在第一底栅极和第二底栅上的栅极电介质上的碳材料，其中碳材料用作LED的沟道区域; 并且金属源极和漏极接触到碳材料。

公开(公告)号：US08866214B2

公开(公告)日：2014-10-21

申请号：US13271812

申请日：2011-10-12

Applicant: Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

Inventor： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L29/78 ,  H01L21/823487 ,  H01L21/823885 ,  H01L29/4983 ,  H01L29/66666 ,  H01L29/7827

Abstract: A transistor structure is formed to include a substrate and, overlying the substrate, a source; a drain; and a channel disposed vertically between the source and the drain. The channel is coupled to a gate conductor that surrounds the channel via a layer of gate dielectric material that surrounds the channel. The gate conductor is composed of a first electrically conductive material having a first work function that surrounds a first portion of a length of the channel and a second electrically conductive material having a second work function that surrounds a second portion of the length of the channel. A method to fabricate the transistor structure is also disclosed. The transistor structure can be characterized as being a vertical field effect transistor having an asymmetric gate.

Abstract translation: 晶体管结构被形成为包括衬底和覆盖衬底的源极; 排水 以及垂直设置在源极和漏极之间的通道。 通道耦合到栅极导体，该栅极导体通过围绕该沟道的栅极电介质材料层围绕该沟道。 栅极导体由具有围绕通道长度的第一部分的第一功函数的第一导电材料和具有围绕通道长度的第二部分的第二功函数的第二导电材料组成。 还公开了制造晶体管结构的方法。 晶体管结构可以表征为具有非对称栅极的垂直场效应晶体管。

公开(公告)号：US08741756B2

公开(公告)日：2014-06-03

申请号：US13584199

申请日：2012-08-13

Applicant: Aaron D. Franklin ,  Shu-jen Han ,  Joshua T. Smith ,  Paul M. Solomon

Inventor： Aaron D. Franklin ,  Shu-jen Han ,  Joshua T. Smith ,  Paul M. Solomon

IPC: H01L21/4763

CPC classification number: B82Y40/00 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775 ,  H01L51/0048 ,  H01L51/055 ,  H01L51/0558

Abstract: A method of fabricating a semiconducting device is disclosed. A carbon nanotube is deposited on a substrate of the semiconducting device. A first contact on the substrate over the carbon nanotube. A second contact on the substrate over the carbon nanotube, wherein the second contact is separated from the first contact by a gap. A portion of the substrate in the gap between the first contact and the second contact is removed.

Abstract translation: 公开了制造半导体器件的方法。 碳纳米管沉积在半导体器件的衬底上。 在碳纳米管上的衬底上的第一接触。 在碳纳米管上的衬底上的第二接触，其中第二接触件通过间隙与第一接触件分离。 第一触点和第二触点之间的间隙中的基板的一部分被去除。