公开(公告)号：US5981378A

公开(公告)日：1999-11-09

申请号：US900501

申请日：1997-07-25

Applicant: Subhas Bothra

Inventor： Subhas Bothra

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763

CPC classification number: H01L21/76876 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10S438/927

Abstract: Disclosed is an aluminum filled via hole for use in a semiconductor interconnect structure. The aluminum filled via hole of the semiconductor interconnect structure includes a first patterned metallization layer lying over a first dielectric layer. A second dielectric layer overlying the first patterned metallization layer and the first dielectric layer. An aluminum filled via hole defined through the second dielectric layer and in contact with the first patterned metallization layer. The aluminum filled via hole has an electromigration barrier cap over a topmost portion of the aluminum filled via hole that is substantially level with the second dielectric layer. The electromigration barrier cap having a thickness of between about 500 angstroms and about 2,500 angstroms.

Abstract translation: 公开了一种用于半导体互连结构的铝填充通孔。 半导体互连结构的铝填充通孔包括位于第一介电层上的第一图案化金属化层。 覆盖第一图案化金属化层和第一介电层的第二电介质层。 通过第二介电层限定并与第一图案化金属化层接触的铝填充通孔。 铝填充的通孔在铝填充的通孔的最上部具有与第二介电层基本平齐的电迁移阻挡帽。 电迁移阻挡盖的厚度介于约500埃至约2500埃之间。

公开(公告)号：US5915203A

公开(公告)日：1999-06-22

申请号：US872562

申请日：1997-06-10

Applicant: Samit Sengupta ,  Subhas Bothra

Inventor： Samit Sengupta ,  Subhas Bothra

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/44

CPC classification number: H01L23/5226 ,  H01L21/76819 ,  H01L21/76885 ,  H01L2924/0002

Abstract: A method of producing deep submicron vias is described in which a metal blanket layer is formed on a premetal dielectric and patterned to form line elements. An intermetal dielectric is then deposited over the patterned metal and chemically mechanically polished down to the top of the line elements. A second metal blanket layer is then deposited and patterned to form via studs. An intermetal dielectric is also deposited over the patterned metal via studs and polished down to the tops of the studs. The process is repeated until a multilevel integrated circuit is formed.

Abstract translation: 描述了生产深亚微米通孔的方法，其中金属覆盖层形成在金属前电介质上并被图案化以形成线元件。 然后将金属间电介质沉积在图案化的金属上，并化学机械地抛光到线元件的顶部。 然后沉积和图案化第二金属覆盖层以形成通孔螺柱。 金属间电介质也通过螺柱沉积在图案化的金属上，并被抛光到螺柱的顶部。 重复该过程，直到形成多层集成电路。

公开(公告)号：US5882997A

公开(公告)日：1999-03-16

申请号：US955030

申请日：1997-10-21

Applicant: Harlan Lee Sur, Jr. ,  Subhas Bothra

Inventor： Harlan Lee Sur, Jr. ,  Subhas Bothra

IPC: G11C11/412 ,  H01L21/02 ,  H01L27/11 ,  H01L21/44

CPC classification number: H01L28/20 ,  G11C11/412 ,  H01L27/1112

Abstract: A resistive load structure and method for making a resistive load structure for an integrated circuit includes the use of an amorphous silicon "antifuse" material. The resistive load structure can be used in an SRAM cell to provide a load to counteract charge leakage at the drains of two pull-down transistors and two pass transistors of the SRAM cell. The resistive load structure is advantageously formed by depositing an amorphous silicon pad over a conductive via, and the resistance of the resistive load structure is controlled by adjusting the thickness of the amorphous silicon pad and varying the diameter of the underlying conductive via.

Abstract translation: 用于制造用于集成电路的电阻负载结构的电阻负载结构和方法包括使用非晶硅“反熔丝”材料。 电阻负载结构可用于SRAM单元中，以提供负载以抵消SRAM单元的两个下拉晶体管和两个通过晶体管的漏极处的电荷泄漏。 有利地通过在导电通孔上沉积非晶硅垫来形成电阻负载结构，并且通过调节非晶硅垫的厚度并改变下面的导电通孔的直径来控制电阻负载结构的电阻。

公开(公告)号：US5877562A

公开(公告)日：1999-03-02

申请号：US925040

申请日：1997-09-08

Applicant: Harlan Sur ,  Subhas Bothra

Inventor： Harlan Sur ,  Subhas Bothra

IPC: G03F9/00 ,  H01L23/544 ,  H01L23/58

CPC classification number: G03F9/708 ,  G03F9/70 ,  G03F9/7084 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002

Abstract: A photo alignment structure integral with a substrate enables the alignment apparatus to receive a reflected light signature of the surface topography of the alignment structure. As the circuit is constructed, the alignment target may be built in tandem with the process. The alignment structure is constructed so that its surface will retain sufficient topography to enable the alignment apparatus to properly align.

Abstract translation: 与基板一体的光取向结构使得对准装置能够接收对准结构的表面形貌的反射光标记。 当构建电路时，可以与该过程一起构建对准目标。 对准结构被构造成使得其表面将保持足够的形貌以使对准装置能够正确对准。

公开(公告)号：US5783488A

公开(公告)日：1998-07-21

申请号：US594874

申请日：1996-01-31

Applicant: Subhas Bothra ,  Milind G. Weling

Inventor： Subhas Bothra ,  Milind G. Weling

IPC: H01L21/3105 ,  H01L21/768 ,  H01L23/522 ,  H01L21/302

CPC classification number: H01L21/31053 ,  H01L21/76819 ,  H01L21/76837 ,  H01L23/522 ,  H01L2924/0002

Abstract: A method of forming sharp oxide peaks on the surface of a semiconductor wafer for the purpose of conditioning polishing pads used during a Chemical Mechanical Polishing process is disclosed. In order to create oxide peaks on the surface of a wafer, additional elements are added to a trace layer of the wafer. An oxide layer is deposited over the additional elements using an Electron Cyclotron Resonance Chemical Vapor Deposition process, which includes a sputtering step, in order to create sharp peaks in the oxide layer over the additional lines. In some embodiments, the additional elements may be formed from a multiplicity of rectangular blocks over which pyramid-like oxide peaks are created. In others, they may be formed from a multiplicity of rectangular blocks connected by narrow lines over which pyramid-like oxide peaks and knife-edged peaks, respectively, are created.

公开(公告)号：US08270629B2

公开(公告)日：2012-09-18

申请号：US11256166

申请日：2005-10-24

Applicant: Subhas Bothra ,  Louis Pandula

Inventor： Subhas Bothra ,  Louis Pandula

IPC: H04R1/10

CPC classification number: H04M1/6058 ,  H04M1/6066 ,  H04M1/72569 ,  H04R5/033 ,  H04R2201/107 ,  H04R2420/01 ,  H04R2420/07 ,  H04R2499/11

Abstract: A system and method allow for safe use of headphones that include a microphone when using the headphones with a cellular phone, a music device, or the like. A desired audio signal, e.g., a voice of a caller or music, is discontinued when a microphone associated with the headphones picks up either a change in ambient noise or a particular type of ambient noise, e.g., an ambulance, a police car, a fire truck, someone yelling, brakes squealing, or the like. During this state, the headphones output either an audible alert signal, the ambient noise, or a pre-stored signal that states “fire,” “police,”, “yelling,” etc. In this way, a person can safely talk on the phone or listen to music when walking or driving, while still being cognizant of what is going on around them.

Abstract translation: 一种系统和方法允许在使用具有蜂窝电话的耳机，音乐设备等时安全地使用包括麦克风的耳机。 当与耳机相关联的麦克风拾取环境噪声的变化或特定类型的环境噪声时，例如救护车，警车，警车等的呼叫者或音乐的所需音频信号，例如呼叫者或音乐的语音， 消防车，有人大喊大叫，刹车尖叫等等。 在这种状态下，耳机输出声音报警信号，环境噪声或预先存储的“火灾”，“警察”，“大喊大叫”等信号。以这种方式，一个人可以安全地说话 在走路或驾驶时，电话或听音乐，同时仍然认识到他们周围发生了什么。

公开(公告)号：US07911310B2

公开(公告)日：2011-03-22

申请号：US12360068

申请日：2009-01-26

Applicant: Carol Barrett ,  Tom McKay ,  Subhas Bothra

Inventor： Carol Barrett ,  Tom McKay ,  Subhas Bothra

IPC: H01F5/00

CPC classification number: H01L23/5227 ,  H01F2017/0046 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors.

Abstract translation: 公开了一种电感器电路。 电感器电路包括第一硅芯片电感器和第二硅芯片电感器，每个具有多个匝数。 第二硅电感器的多圈的一部分形成在第一硅内感应器的匝之间。 第一和第二硅内电感器被配置为使得流过第一硅芯片电感器和第二硅芯片电感器的差分电流在相应的电感圈中以相同的方向流动。

公开(公告)号：US07434189B2

公开(公告)日：2008-10-07

申请号：US11254903

申请日：2005-10-20

Applicant: Donald Baumann ,  Subhas Bothra

Inventor： Donald Baumann ,  Subhas Bothra

IPC: G06F17/50

CPC classification number: H01L27/0203 ,  H01L23/5286 ,  H01L24/06 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00

Abstract: Embodiments of the present invention provide an integrated circuit (IC) in which power to input output (IO) drivers may be distributed within unused areas over macro processing circuits. This IC includes a long distance power and ground distribution network, an input output (IO) power and ground distribution network, a number of macro processing circuits, and IO circuits. The long distance power and ground distribution network electrically couples to the IO power and ground distribution network. Both the power and ground distribution networks may be located within the upper level conductive layers. IO power and ground distribution network locally supplies power and ground to IO circuits. Macro processing circuits may be located beneath the power distribution network as some macro processing circuits do not require access to upper level conductive layers. By placing these macro processing circuits beneath these power distribution networks, die size may be reduced.

Abstract translation: 本发明的实施例提供一种集成电路（IC），其中输入输出（IO）驱动器的功率可以通过宏处理电路分布在未使用的区域内。 该IC包括长距离电源和地面分配网络，输入输出（IO）电源和地面分配网络，多个宏处理电路和IO电路。 长距离电力和地面分配网络电耦合到IO电力和地面分配网络。 电力和地面分布网络都可以位于上层导电层内。 IO电源和地面分配网络本地为IO电路供电和接地。 宏处理电路可以位于配电网下方，因为一些宏处理电路不需要访问上层导电层。 通过将这些宏处理电路放置在这些配电网络的下方，可以减小管芯尺寸。

公开(公告)号：US20070090401A1

公开(公告)日：2007-04-26

申请号：US11254903

申请日：2005-10-20

Applicant: Donald Baumann ,  Subhas Bothra

Inventor： Donald Baumann ,  Subhas Bothra

IPC: H01L27/10

CPC classification number: H01L27/0203 ,  H01L23/5286 ,  H01L24/06 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00

Abstract: Embodiments of the present invention provide an integrated circuit (IC) in which power to input output (IO) drivers may be distributed within unused areas over macro processing circuits. This IC includes a long distance power and ground distribution network, an input output (IO) power and ground distribution network, a number of macro processing circuits, and IO circuits. The long distance power and ground distribution network electrically couples to the IO power and ground distribution network. Both the power and ground distribution networks may be located within the upper level conductive layers. IO power and ground distribution network locally supplies power and ground to IO circuits. Macro processing circuits may be located beneath the power distribution network as some macro processing circuits do not require access to upper level conductive layers. By placing these macro processing circuits beneath these power distribution networks, die size may be reduced.

Abstract translation: 本发明的实施例提供一种集成电路（IC），其中输入输出（IO）驱动器的功率可以通过宏处理电路分布在未使用的区域内。 该IC包括长距离电源和地面分配网络，输入输出（IO）电源和地面分配网络，多个宏处理电路和IO电路。 长距离电力和地面分配网络电耦合到IO电力和地面分配网络。 电力和地面分布网络都可以位于上层导电层内。 IO电源和地面分配网络本地为IO电路供电和接地。 宏处理电路可以位于配电网下方，因为一些宏处理电路不需要访问上层导电层。 通过将这些宏处理电路放置在这些配电网络的下方，可以减小管芯尺寸。

公开(公告)号：US06916525B2

公开(公告)日：2005-07-12

申请号：US10666484

申请日：2003-09-19

Applicant: Subhas Bothra ,  Milind G. Weling

Inventor： Subhas Bothra ,  Milind G. Weling

IPC: B24B37/013 ,  B24B49/10 ,  H01L21/3105 ,  B32B9/04 ,  B32B3/00

CPC classification number: B24B37/013 ,  B24B49/10 ,  H01L21/31053 ,  Y10T428/24917

Abstract: A method of using films having optimized optical properties for chemical mechanical polishing (CMP) endpoint detection. Specifically, one embodiment of the present invention includes a method for improving chemical mechanical polishing endpoint detection. The method comprises the step of depositing a dielectric layer over a reflectance stop layer. The reflectance stop layer is disposed above a component that is disposed on a semiconductor wafer. During a determination of the thickness of the dielectric layer using a reflected signal of light, the reflectance stop layer substantially reduces any light from reflecting off of the component. Therefore, the present invention provides a method and system that provides more accurate endpoint detection during a CMP process of semiconductor wafers. As a result of the present invention, an operator of a CMP machine knows precisely when to stop a CMP process of a semiconductor wafer. Furthermore, the present invention enables the operator of the CMP machine to know within a certain accuracy the film (e.g., dielectric layer) thickness remaining after the CMP process of the semiconductor wafer. Moreover, the present invention essentially eliminates excessive chemical mechanical polishing of the semiconductor wafer. As such, not as much dielectric material needs to be deposited on the wafer in order to compensate for excessive chemical mechanical polishing of the semiconductor wafer. Therefore, the present invention is able to reduce fabrication costs of semiconductor wafers.

Abstract translation: 使用具有优化的光学性质的膜用于化学机械抛光（CMP）端点检测的方法。 具体地，本发明的一个实施方案包括用于改进化学机械抛光终点检测的方法。 该方法包括在反射停止层上沉积介电层的步骤。 反射阻挡层设置在配置在半导体晶片上的部件的上方。 在使用光的反射信号确定介电层的厚度期间，反射率停止层基本上减少了从组件反射的任何光。 因此，本发明提供了一种在半导体晶片的CMP工艺期间提供更准确的端点检测的方法和系统。 作为本发明的结果，CMP机器的操作者精确地知道何时停止半导体晶片的CMP工艺。 此外，本发明使得CMP机器的操作者能够在半导体晶片的CMP处理之后以一定的精度了解剩余的膜（例如介电层）的厚度。 此外，本发明基本上消除了半导体晶片的过度的化学机械抛光。 因此，为了补偿半导体晶片的过度的化学机械抛光，不需要在晶片上沉积太多的介电材料。 因此，本发明能够降低半导体晶片的制造成本。